Inventor
SONGER NEIL W
US20 patents
⚠️ This page may combine multiple inventors who share the name “SONGER NEIL W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS6438622B1Aug 20, 2002
Multiprocessor system including a docking system
INTEL CORP224 citations98
US6041372AMar 21, 2000
Method and apparatus for providing a processor module for a computer system
INTEL CORP64 citations95
US5729762AMar 17, 1998
Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
INTEL CORP55 citations95
US5862387AJan 19, 1999
Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller
INTEL CORP83 citations94
US5664197ASep 2, 1997
Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller
INTEL CORP71 citations93
US5983297ANov 9, 1999
Method and apparatus for upgrading a computer system
INTEL CORP31 citations91
US9874922B2Jan 23, 2018
Performing dynamic power control of platform devices
INTEL CORP5 citations73
US9838967B2Dec 5, 2017
Downstream device service latency reporting for power management
INTEL CORP2 citations73
US9195292B2Nov 24, 2015
Controlling reduced power states using platform latency tolerance
INTEL CORP2 citations61
US10761579B2Sep 1, 2020
Supercapacitor-based power supply protection for multi-node systems
INTEL CORP0 citations52
US10678199B2Jun 9, 2020
Systems, methods and devices for standby power entry without latency tolerance information
INTEL CORP0 citations52
US10182398B2Jan 15, 2019
Downstream device service latency reporting for power management
INTEL CORP0 citations52
US9766673B2Sep 19, 2017
Supercapacitor-based power supply protection for multi-node systems
INTEL CORP0 citations52
US9459684B2Oct 4, 2016
Idle duration reporting for power management
INTEL CORP0 citations52
US9541983B2Jan 10, 2017
Controlling reduced power states using platform latency tolerance
INTEL CORP0 citations51
US10146290B2Dec 4, 2018
Platform communication protocol
INTEL CORP0 citations50