Inventor

QUESTAD DAVID L

US57 patents

⚠️ This page may combine multiple inventors who share the name “QUESTAD DAVID L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QUESTAD DAVID L

IBM

Method of forming a flip chip assembly

Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging

Design structure for final via designs for chip stress reduction

Flip chip assembly

Method of forming a flip chip assembly, and a flip chip assembly formed by the method

Unique feature design enabling structural integrity for advanced low K semiconductor chips

Final via structures for bond pad-solder ball interconnections

Sandwiched organic LGA structure

Chip underfill in flip-chip technologies

Apparatus and method for mechanical coupling of land grid array applications

Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package

Unique feature design enabling structural integrity for advanced low k semiconductor chips

Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages

Heat sink attachment on existing heat sinks

Heat sink attachment on existing heat sinks

Process for chemically and mechanically enhancing solder surface properties

Method and apparatus for strain relieving surface mount attached connectors

Method and apparatus for strain relieving surface mount attached connectors

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

Semiconductor package having non-aligned active vias

Method of forming a flip-chip package

Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners

Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages

Fixture to constrain laminate and method of assembly

Solder ball with chemically and mechanically enhanced surface properties

Enhanced via structure for organic module performance

Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners

Strengthening of a structure by infiltration

Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity

Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity

Fixture to constrain laminate and method of assembly

Enhanced solder surface and process for chemically and mechanically enhancing solder surface properties

Method and apparatus for strain relieving surface mount attached connectors

Test cell for laminate and method

Test cell for laminate and method

KACKER KARAN

Clustered stacked vias for reliable electronic substrates

Clustered stacked vias for reliable electronic substrates

Construction of reliable stacked via in electronic substrates—vertical stiffness control method

Construction of reliable stacked via in electronic substrates—vertical stiffness control method

Construction of reliable stacked via in electronic substrates—vertical stiffness control method

DAUBENSPECK TIMOTHY H

Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump

Structures and methods to improve lead-free C4 interconnect reliability

Offset solder vias, methods of manufacturing and design structures

LU MINHUA

Robust FBEOL and UBM structure of C4 interconnects

Robust FBEOL and UBM structure of C4 interconnects

ARVIN CHARLES L

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

PERFECTO ERIC DAVID

Dimensionally decoupled ball limiting metalurgy

INTERNAT BUSINESS MACHIENS COR

Design structure for final via designs for chip stress reduction

BERNIER WILLIAM E

Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity

BONILLA GRISELDA

Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections