Inventor
IADONATO KEVIN R
US26 patents
⚠️ This page may combine multiple inventors who share the name “IADONATO KEVIN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SEIKO EPSON CORP
25 patentsUS5497499AMar 5, 1996
Superscalar risc instruction scheduling
SEIKO EPSON CORP120 citations99
US6360309B1Mar 19, 2002
System and method for assigning tags to control instruction processing in a superscalar processor
SEIKO EPSON CORP36 citations96
US6138231AOct 24, 2000
System and method for register renaming
SEIKO EPSON CORP24 citations96
US5896542AApr 20, 1999
System and method for assigning tags to control instruction processing in a superscalar processor
SEIKO EPSON CORP30 citations96
US5809276ASep 15, 1998
System and method for register renaming
SEIKO EPSON CORP26 citations96
US5734584AMar 31, 1998
Integrated structure layout and layout of interconnections for an integrated circuit chip
SEIKO EPSON CORP27 citations96
US5628021AMay 6, 1997
System and method for assigning tags to control instruction processing in a superscalar processor
SEIKO EPSON CORP34 citations96
US5604912AFeb 18, 1997
System and method for assigning tags to instructions to control instruction execution
SEIKO EPSON CORP62 citations96
US5590295ADec 31, 1996
System and method for register renaming
SEIKO EPSON CORP66 citations96
US5371684ADec 6, 1994
Semiconductor floor plan for a register renaming circuit
SEIKO EPSON CORP63 citations96
US6782521B2Aug 24, 2004
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
SEIKO EPSON CORP21 citations93
US6401232B1Jun 4, 2002
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
SEIKO EPSON CORP19 citations93
US6083274AJul 4, 2000
Integrated structure layout and layout of interconnections for an integrated circuit chip
SEIKO EPSON CORP18 citations93
US5831871ANov 3, 1998
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
SEIKO EPSON CORP21 citations93
US5566385AOct 15, 1996
Integrated structure layout and layout of interconnections for an integrated circuit chip
SEIKO EPSON CORP22 citations93
US7558945B2Jul 7, 2009
System and method for register renaming
SEIKO EPSON CORP8 citations92
US7043624B2May 9, 2006
System and method for assigning tags to control instruction processing in a superscalar processor
SEIKO EPSON CORP13 citations92
US6970995B2Nov 29, 2005
System and method for register renaming
SEIKO EPSON CORP12 citations92
US6922772B2Jul 26, 2005
System and method for register renaming
SEIKO EPSON CORP12 citations92
US6757808B2Jun 29, 2004
System and method for assigning tags to control instruction processing in a superscalar processor
SEIKO EPSON CORP19 citations92
US6272617B1Aug 7, 2001
System and method for register renaming
SEIKO EPSON CORP21 citations92
US6092176AJul 18, 2000
System and method for assigning tags to control instruction processing in a superscalar processor
SEIKO EPSON CORP22 citations92
US6408375B2Jun 18, 2002
System and method for register renaming
SEIKO EPSON CORP13 citations82
US7979678B2Jul 12, 2011
System and method for register renaming
SEIKO EPSON CORP5 citations74
US7430651B2Sep 30, 2008
System and method for assigning tags to control instruction processing in a superscalar processor
SEIKO EPSON CORP2 citations63