Inventor

KADIYALA SURESH

US11 patents

⚠️ This page may combine multiple inventors who share the name “KADIYALA SURESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DURBHA ANANTH

3 patents

US8572544B2Oct 29, 2013

Programmatic auto-convergent method for “physical layout power hot-spot” risk aware ASIP architecture customization for performance optimization

DURBHA ANANTH5 citations82

US8561005B2Oct 15, 2013

Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design

DURBHA ANANTH4 citations60

US8185862B2May 22, 2012

Architectural level power-aware optimization and risk mitigation

DURBHA ANANTH4 citations60

NG PIUS

2 patents

US8484588B2Jul 9, 2013

System, architecture and micro-architecture (SAMA) representation of an integrated circuit

NG PIUS10 citations81

US8589854B2Nov 19, 2013

Application driven power gating

NG PIUS1 citations48

NETXEN INC

1 patent

US7493481B1Feb 17, 2009

Direct hardware processing of internal data structure fields

NETXEN INC30 citations88

KIZHEPAT GOVIND

1 patent

US8555260B1Oct 8, 2013

Direct hardware processing of internal data structure fields

KIZHEPAT GOVIND6 citations80

PANDURANGAN ANAND

1 patent

US8423929B2Apr 16, 2013

Intelligent architecture creator

PANDURANGAN ANAND2 citations57

ALGOTOCHIP CORP

1 patent

US8370784B2Feb 5, 2013

Automatic optimal integrated circuit generator from algorithms and specification

ALGOTOCHIP CORP4 citations52

KADIYALA SURESH

1 patent

US8336017B2Dec 18, 2012

Architecture optimizer

KADIYALA SURESH4 citations51

PADMANABHAN SATISH

1 patent

US8225247B2Jul 17, 2012

Automatic optimal integrated circuit generator from algorithms and specification

PADMANABHAN SATISH0 citations42