Inventor

EITAN BOAZ

IL130 patents

⚠️ This page may combine multiple inventors who share the name “EITAN BOAZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EITAN BOAZ

SAIFUN SEMICONDUCTORS LTD

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Method for erasing a memory cell

Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Programming and erasing methods for a reference cell of an NROM array

NROM cell with improved programming, erasing and cycling

NROM cell with generally decoupled primary and secondary injection

NROM cell with self-aligned programming and erasure areas

Method for programming of a semiconductor memory cell

NROM cell with improved programming, erasing and cycling

Two bit ROM cell and process for producing same

Method for initiating a retrieval procedure in virtual ground arrays

Process for producing two bit ROM cell utilizing angled implant

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

NROM fabrication method with a periphery portion

Symmetric segmented memory array architecture

Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping

Programming of nonvolatile memory cells

Method and apparatus for operating with a close to ground signal

Programming and erasing methods for a non-volatile memory cell

Method for operation of an EEPROM array, including refresh thereof

Architecture and scheme for a non-strobed read sequence

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Multiple use memory chip

NROM NOR array

Programming of nonvolatile memory cells

Method for operating a memory device

NROM cell with self-aligned programming and erasure areas

Symmetric architecture for memory cells having widely spread metal bit lines

Method and circuit for minimizing the charging effect during manufacture of semiconductor devices

EEPROM array and method for operation thereof

Reducing secondary injection effects

Method for programming a reference cell

Symmetric segmented memory array architecture

Symmetric segmented memory array architecture

Device for determining the validity of word line conditions and for delaying data sensing operation

Programming and erasing methods for a non-volatile memory cell

WAFERSCALE INTEGRATION INC

Backup battery switch

Fast EPROM array

Low power programmable ring oscillator

Electrically programmable read only memory array

Eprom virtual ground array

Method for programming a floating gate memory device

Nonvolatile floating gate transistor structure

Single layer polycrystalline floating gate

Self-aligned split gate EPROM

Unit for stabilizing voltage on a capacitive node

SAIFUN SEMICONDUCTOR LTD

Method, system and circuit for programming a non-volatile memory array

SAIFUN SEMICINDUCTORS LTD

Method and circuit for minimizing the charging effect during manufacture of semiconductor devices