Inventor

ZHOU MEI-SHENG

SG145 patents

Patents

50 patents

US6475908B1Nov 5, 2002

Dual metal gate process: metals and their silicides

CHARTERED SEMICONDUCTOR MFG128 citations99

US6436824B1Aug 20, 2002

Low dielectric constant materials for copper damascene

CHARTERED SEMICONDUCTOR MFG175 citations99

US6376353B1Apr 23, 2002

Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects

CHARTERED SEMICONDUCTOR MFG319 citations99

US6348407B1Feb 19, 2002

Method to improve adhesion of organic dielectrics in dual damascene interconnects

CHARTERED SEMICONDUCTOR MFG250 citations99

US6284657B1Sep 4, 2001

Methods to form dual metal gates by incorporating metals and their conductive oxides

CHARTERED SEMICONDUCTOR MFG83 citations98

US6380087B1Apr 30, 2002

CMP process utilizing dummy plugs in damascene process

CHARTERED SEMICONDUCTOR MFG89 citations98

US6358842B1Mar 19, 2002

Method to form damascene interconnects with sidewall passivation to protect organic dielectrics

CHARTERED SEMICONDUCTOR MFG141 citations98

US6352917B1Mar 5, 2002

Reversed damascene process for multiple level metal interconnects

CHARTERED SEMICONDUCTOR MFG140 citations98

US6287979B1Sep 11, 2001

Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer

CHARTERED SEMICONDUCTOR MFG140 citations98

US6274499B1Aug 14, 2001

Method to avoid copper contamination during copper etching and CMP

CHARTERED SEMICONDUCTOR MFG98 citations98

US6184138B1Feb 6, 2001

Method to create a controllable and reproducible dual copper damascene structure

CHARTERED SEMICONDUCTOR MFG121 citations98

US6165891ADec 26, 2000

Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer

CHARTERED SEMICONDUCTOR MFG87 citations98

US6114243ASep 5, 2000

Method to avoid copper contamination on the sidewall of a via or a dual damascene structure

CHARTERED SEMICONDUCTOR MFG123 citations98

US6040243AMar 21, 2000

Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion

CHARTERED SEMICONDUCTOR MFG250 citations98

US6632712B1Oct 14, 2003

Method of fabricating variable length vertical transistors

CHARTERED SEMICONDUCTOR MFG89 citations97

US6331479B1Dec 18, 2001

Method to prevent degradation of low dielectric constant material in copper damascene interconnects

CHARTERED SEMICONDUCTOR MFG84 citations97

US5863307AJan 26, 1999

Method and slurry composition for chemical-mechanical polish (CMP) planarizing of copper containing conductor layers

CHARTERED SEMICONDUCTOR MFG91 citations97

US5801083ASep 1, 1998

Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners

CHARTERED SEMICONDUCTOR MFG251 citations97

US6750519B2Jun 15, 2004

Dual metal gate process: metals and their silicides

CHARTERED SEMICONDUCTOR MFG45 citations96

US6566260B2May 20, 2003

Non-metallic barrier formations for copper damascene type interconnects

CHARTERED SEMICONDUCTOR MFG32 citations96

US6489233B2Dec 3, 2002

Non-metallic barrier formations for copper damascene type interconnects

CHARTERED SEMICONDUCTOR MFG36 citations96

US6486080B2Nov 26, 2002

Method to form zirconium oxide and hafnium oxide for high dielectric constant materials

CHARTERED SEMICONDUCTOR MFG65 citations96

US6424044B1Jul 23, 2002

Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization

CHARTERED SEMICONDUCTOR MFG99 citations96

US6372636B1Apr 16, 2002

Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene

CHARTERED SEMICONDUCTOR MFG70 citations96

US6251786B1Jun 26, 2001

Method to create a copper dual damascene structure with less dishing and erosion

CHARTERED SEMICONDUCTOR MFG65 citations96

US6121130ASep 19, 2000

Laser curing of spin-on dielectric thin films

CHARTERED SEMICONDUCTOR MFG118 citations96

US6352921B1Mar 5, 2002

Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization

CHARTERED SEMICONDUCTOR MFG64 citations95

US6303447B1Oct 16, 2001

Method for forming an extended metal gate using a damascene process

CHARTERED SEMICONDUCTOR MFG51 citations95

US6225221B1May 1, 2001

Method to deposit a copper seed layer for dual damascene interconnects

CHARTERED SEMICONDUCTOR MFG53 citations95

US6228713B1May 8, 2001

Self-aligned floating gate for memory application using shallow trench isolation

CHARTERED SEMICONDUCTOR MFG64 citations94

US6009888AJan 4, 2000

Photoresist and polymer removal by UV laser aqueous oxidant

CHARTERED SEMICONDUCTOR MFG62 citations94

US5866448AFeb 2, 1999

Procedure for forming a lightly-doped-drain structure using polymer layer

CHARTERED SEMICONDUCTOR MFG58 citations94

US5780358AJul 14, 1998

Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers

CHARTERED SEMICONDUCTOR MFG132 citations94

US7005716B2Feb 28, 2006

Dual metal gate process: metals and their silicides

CHARTERED SEMICONDUCTOR MFG25 citations93

US6690091B1Feb 10, 2004

Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer

CHARTERED SEMICONDUCTOR MFG29 citations93

US6677652B2Jan 13, 2004

Methods to form dual metal gates by incorporating metals and their conductive oxides

CHARTERED SEMICONDUCTOR MFG24 citations93

US6350675B1Feb 26, 2002

Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects

CHARTERED SEMICONDUCTOR MFG55 citations93

US6156598ADec 5, 2000

Method for forming a lightly doped source and drain structure using an L-shaped spacer

CHARTERED SEMICONDUCTOR MFG51 citations93

US6740580B1May 25, 2004

Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier

CHARTERED SEMICONDUCTOR MFG40 citations92

US6720204B2Apr 13, 2004

Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding

CHARTERED SEMICONDUCTOR MFG38 citations92

US6531390B2Mar 11, 2003

Non-metallic barrier formations for copper damascene type interconnects

CHARTERED SEMICONDUCTOR MFG19 citations92

US6524963B1Feb 25, 2003

Method to improve etching of organic-based, low dielectric constant materials

CHARTERED SEMICONDUCTOR MFG24 citations92

US6475810B1Nov 5, 2002

Method of manufacturing embedded organic stop layer for dual damascene patterning

CHARTERED SEMICONDUCTOR MFG24 citations92

US6465888B2Oct 15, 2002

Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene

CHARTERED SEMICONDUCTOR MFG33 citations92

US6429117B1Aug 6, 2002

Method to create copper traps by modifying treatment on the dielectrics surface

CHARTERED SEMICONDUCTOR MFG21 citations92

US6429122B2Aug 6, 2002

Non metallic barrier formations for copper damascene type interconnects

CHARTERED SEMICONDUCTOR MFG25 citations92

US6417088B1Jul 9, 2002

Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding

CHARTERED SEMICONDUCTOR MFG44 citations92

Showing the top 50 of 145 patents by PatentIndex Score.

ZHOU MEI-SHENG

Patents

Dual metal gate process: metals and their silicides

Low dielectric constant materials for copper damascene

Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects

Method to improve adhesion of organic dielectrics in dual damascene interconnects

Non-metallic barrier formation for copper damascene type interconnects

Air bridge process for forming air gaps

Method to create a copper diffusion deterrent interface

Methods to form dual metal gates by incorporating metals and their conductive oxides

CMP process utilizing dummy plugs in damascene process

Method to form damascene interconnects with sidewall passivation to protect organic dielectrics

Reversed damascene process for multiple level metal interconnects

Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer

Method to avoid copper contamination during copper etching and CMP

Method to create a controllable and reproducible dual copper damascene structure

Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer

Method to avoid copper contamination on the sidewall of a via or a dual damascene structure

Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion

Method of fabricating variable length vertical transistors

Method to prevent degradation of low dielectric constant material in copper damascene interconnects

Method and slurry composition for chemical-mechanical polish (CMP) planarizing of copper containing conductor layers

Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners

Dual metal gate process: metals and their silicides

Non-metallic barrier formations for copper damascene type interconnects

Non-metallic barrier formations for copper damascene type interconnects

Method to form zirconium oxide and hafnium oxide for high dielectric constant materials

Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization

Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene

Method to create a copper dual damascene structure with less dishing and erosion

Laser curing of spin-on dielectric thin films

Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization

Method for forming an extended metal gate using a damascene process

Method to deposit a copper seed layer for dual damascene interconnects

Self-aligned floating gate for memory application using shallow trench isolation

Photoresist and polymer removal by UV laser aqueous oxidant

Procedure for forming a lightly-doped-drain structure using polymer layer

Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers

Dual metal gate process: metals and their silicides

Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer

Methods to form dual metal gates by incorporating metals and their conductive oxides

Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects

Method for forming a lightly doped source and drain structure using an L-shaped spacer

Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier

Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding

Non-metallic barrier formations for copper damascene type interconnects

Method to improve etching of organic-based, low dielectric constant materials

Method of manufacturing embedded organic stop layer for dual damascene patterning

Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene

Method to create copper traps by modifying treatment on the dielectrics surface

Non metallic barrier formations for copper damascene type interconnects

Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding