Inventor
CHOOI SIMON
SG92 patents
Patents
50 patentsUS6475908B1Nov 5, 2002
Dual metal gate process: metals and their silicides
CHARTERED SEMICONDUCTOR MFG128 citations99
US6436824B1Aug 20, 2002
Low dielectric constant materials for copper damascene
CHARTERED SEMICONDUCTOR MFG175 citations99
US6376353B1Apr 23, 2002
Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
CHARTERED SEMICONDUCTOR MFG319 citations99
US6348407B1Feb 19, 2002
Method to improve adhesion of organic dielectrics in dual damascene interconnects
CHARTERED SEMICONDUCTOR MFG250 citations99
US6284657B1Sep 4, 2001
Non-metallic barrier formation for copper damascene type interconnects
CHARTERED SEMICONDUCTOR MFG190 citations99
US6265321B1Jul 24, 2001
Air bridge process for forming air gaps
CHARTERED SEMICONDUCTOR MFG148 citations99
US6683002B1Jan 27, 2004
Method to create a copper diffusion deterrent interface
CHARTERED SEMICONDUCTOR MFG71 citations98
US6458695B1Oct 1, 2002
Methods to form dual metal gates by incorporating metals and their conductive oxides
CHARTERED SEMICONDUCTOR MFG83 citations98
US6358842B1Mar 19, 2002
Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
CHARTERED SEMICONDUCTOR MFG141 citations98
US6352917B1Mar 5, 2002
Reversed damascene process for multiple level metal interconnects
CHARTERED SEMICONDUCTOR MFG140 citations98
US6287979B1Sep 11, 2001
Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer
CHARTERED SEMICONDUCTOR MFG140 citations98
US6165891ADec 26, 2000
Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
CHARTERED SEMICONDUCTOR MFG87 citations98
US6114243ASep 5, 2000
Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
CHARTERED SEMICONDUCTOR MFG123 citations98
US6040243AMar 21, 2000
Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
CHARTERED SEMICONDUCTOR MFG250 citations98
US6331479B1Dec 18, 2001
Method to prevent degradation of low dielectric constant material in copper damascene interconnects
CHARTERED SEMICONDUCTOR MFG84 citations97
US6750519B2Jun 15, 2004
Dual metal gate process: metals and their silicides
CHARTERED SEMICONDUCTOR MFG45 citations96
US6566260B2May 20, 2003
Non-metallic barrier formations for copper damascene type interconnects
CHARTERED SEMICONDUCTOR MFG32 citations96
US6489233B2Dec 3, 2002
Non-metallic barrier formations for copper damascene type interconnects
CHARTERED SEMICONDUCTOR MFG36 citations96
US6486080B2Nov 26, 2002
Method to form zirconium oxide and hafnium oxide for high dielectric constant materials
CHARTERED SEMICONDUCTOR MFG65 citations96
US6424044B1Jul 23, 2002
Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization
CHARTERED SEMICONDUCTOR MFG99 citations96
US6372636B1Apr 16, 2002
Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
CHARTERED SEMICONDUCTOR MFG70 citations96
US6352921B1Mar 5, 2002
Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization
CHARTERED SEMICONDUCTOR MFG64 citations95
US6303447B1Oct 16, 2001
Method for forming an extended metal gate using a damascene process
CHARTERED SEMICONDUCTOR MFG51 citations95
US7005716B2Feb 28, 2006
Dual metal gate process: metals and their silicides
CHARTERED SEMICONDUCTOR MFG25 citations93
US6690091B1Feb 10, 2004
Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer
CHARTERED SEMICONDUCTOR MFG29 citations93
US6677652B2Jan 13, 2004
Methods to form dual metal gates by incorporating metals and their conductive oxides
CHARTERED SEMICONDUCTOR MFG24 citations93
US6350675B1Feb 26, 2002
Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects
CHARTERED SEMICONDUCTOR MFG55 citations93
US6762085B2Jul 13, 2004
Method of forming a high performance and low cost CMOS device
CHARTERED SEMICONDUCTOR MFG36 citations92
US6720204B2Apr 13, 2004
Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding
CHARTERED SEMICONDUCTOR MFG38 citations92
US6534388B1Mar 18, 2003
Method to reduce variation in LDD series resistance
CHARTERED SEMICONDUCTOR MFG37 citations92
US6531386B1Mar 11, 2003
Method to fabricate dish-free copper interconnects
CHARTERED SEMICONDUCTOR MFG23 citations92
US6531390B2Mar 11, 2003
Non-metallic barrier formations for copper damascene type interconnects
CHARTERED SEMICONDUCTOR MFG19 citations92
US6524963B1Feb 25, 2003
Method to improve etching of organic-based, low dielectric constant materials
CHARTERED SEMICONDUCTOR MFG24 citations92
US6475810B1Nov 5, 2002
Method of manufacturing embedded organic stop layer for dual damascene patterning
CHARTERED SEMICONDUCTOR MFG24 citations92
US6465888B2Oct 15, 2002
Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
CHARTERED SEMICONDUCTOR MFG33 citations92
US6429122B2Aug 6, 2002
Non metallic barrier formations for copper damascene type interconnects
CHARTERED SEMICONDUCTOR MFG25 citations92
US6429117B1Aug 6, 2002
Method to create copper traps by modifying treatment on the dielectrics surface
CHARTERED SEMICONDUCTOR MFG21 citations92
US6417088B1Jul 9, 2002
Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding
CHARTERED SEMICONDUCTOR MFG44 citations92
US6394114B1May 28, 2002
Method for stripping copper in damascene interconnects
CHARTERED SEMICONDUCTOR MFG20 citations92
US6387765B2May 14, 2002
Method for forming an extended metal gate using a damascene process
CHARTERED SEMICONDUCTOR MFG19 citations92
US6378759B1Apr 30, 2002
Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding
CHARTERED SEMICONDUCTOR MFG37 citations92
US6340608B1Jan 22, 2002
Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads
CHARTERED SEMICONDUCTOR MFG21 citations92
US6261942B1Jul 17, 2001
Dual metal-oxide layer as air bridge
CHARTERED SEMICONDUCTOR MFG42 citations92
US5948701ASep 7, 1999
Self-aligned contact (SAC) etching using polymer-building chemistry
CHARTERED SEMICONDUCTOR MFG32 citations92
US6271115B1Aug 7, 2001
Post metal etch photoresist strip method
CHARTERED SEMICONDUCTOR MFG21 citations91
US6376361B1Apr 23, 2002
Method to remove excess metal in the formation of damascene and dual interconnects
CHARTERED SEMICONDUCTOR MFG33 citations90
US6797605B2Sep 28, 2004
Method to improve adhesion of dielectric films in damascene interconnects
CHARTERED SEMICONDUCTOR MFG17 citations89
US6530380B1Mar 11, 2003
Method for selective oxide etching in pre-metal deposition
CHARTERED SEMICONDUCTOR MFG40 citations88
US6891233B2May 10, 2005
Methods to form dual metal gates by incorporating metals and their conductive oxides
CHARTERED SEMICONDUCTOR MFG15 citations84
US6540841B1Apr 1, 2003
Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate
CHARTERED SEMICONDUCTOR MFG13 citations84
Showing the top 50 of 92 patents by PatentIndex Score.