Inventor

WEI ANDY CHIH-HUNG

US50 patents

⚠️ This page may combine multiple inventors who share the name “WEI ANDY CHIH-HUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEI ANDY CHIH-HUNG

GLOBALFOUNDRIES INC

Self-aligned via and air gap

Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme

Transistor contacts self-aligned in two dimensions

Self-aligned back end of line cut

Self-aligned back end of line cut

Precut metal lines

Semiconductor structure having gap fill dielectric layer disposed between fins

Self-aligned gate contact formation

Opposite polarity borderless replacement metal contact scheme

Method for creating self-aligned transistor contacts

Metal gate structure and method of formation

Precut metal lines

Merged gate and source/drain contacts in a semiconductor device

Self-aligned via and air gap

Transistor contacts self-aligned two dimensions

Semiconductor contacts and methods of fabrication

Borderless contact formation through metal-recess dual cap integration

Split well zero threshold voltage field effect transistor for integrated circuits

Patterning multiple, dense features in a semiconductor device using a memorization layer

Multiple fin finFET with low-resistance gate structure

Method of forming semiconductor fins

Multiple fin finFET with low-resistance gate structure

Merged gate and source/drain contacts in a semiconductor device

Transistor contacts self-aligned in two dimensions

Method for creating self-aligned transistor contacts

INTEL CORP

Stacked vias with bottom portions formed using selective growth

Gate spacing in integrated circuit structures

Power rail between fins of a transistor structure

Gate-all-around integrated circuit structures having germanium-diffused nanoribbon channel structures

Gate tie structures to buried or backside power rails

Source/drain regions in integrated circuit structures

Gate spacing in integrated circuit structures

Device contact sizing in integrated circuit structures

Source/drain regions in integrated circuit structures

Isolation regions in integrated circuit structures

Source/drain regions in integrated circuit structures

Device contact sizing in integrated circuit structures

Isolation regions in integrated circuit structures

Self-aligned lateral contacts

Device contacts in integrated circuit structures

Integrated circuit structures with gate cuts above buried power rails

Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication

Use of a placeholder for backside contact formation for transistor arrangements

Back end of line integration for self-aligned vias

Integrated circuit structures having maximized channel sizing

Buried power rails with self-aligned vias to trench contacts

Dual metal gate structures on nanoribbon semiconductor devices

Transistor arrangements with stacked trench contacts and gate straps

Transistor arrangements with metal gate cuts and recessed power rails

Intel NDTM US LLC

Stitching to enable dense interconnect arrangements