Inventor
DUNN BERGER DEANNA POSTLES
US11 patents
⚠️ This page may combine multiple inventors who share the name “DUNN BERGER DEANNA POSTLES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
5 patentsUS8996819B2Mar 31, 2015
Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy
IBM4 citations72
US10540251B2Jan 21, 2020
Accuracy sensitive performance counters
IBM2 citations71
US8352687B2Jan 8, 2013
Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy
IBM4 citations62
US10884890B2Jan 5, 2021
Accuracy sensitive performance counters
IBM0 citations60
US8706972B2Apr 22, 2014
Dynamic mode transitions for cache instructions
IBM0 citations51
DUNN BERGER DEANNA POSTLES
5 patentsUS8566532B2Oct 22, 2013
Management of multipurpose command queues in a multilevel cache hierarchy
DUNN BERGER DEANNA POSTLES4 citations60
US8407420B2Mar 26, 2013
System, apparatus and method utilizing early access to shared cache pipeline for latency reduction
DUNN BERGER DEANNA POSTLES2 citations60
US8635409B2Jan 21, 2014
Dynamic mode transitions for cache instructions
DUNN BERGER DEANNA POSTLES0 citations50
US8407442B2Mar 26, 2013
Preemptive in-pipeline store compare resolution
DUNN BERGER DEANNA POSTLES0 citations50
US8539190B2Sep 17, 2013
Preemptive in-pipeline store compare resolution
DUNN BERGER DEANNA POSTLES0 citations45