Inventor

WALTERS CRAIG R

US49 patents

⚠️ This page may combine multiple inventors who share the name “WALTERS CRAIG R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WALTERS CRAIG R

IBM

Process of operations with an interchangeable transmission device and apparatus for use therein for a common interface for use with digital cameras

Distributed shared resource management

Controller address contention assumption

Multiple copy scoping bits for cache memory

Speculative data return concurrent to an exclusive invalidate request

Predictive scheduler for memory rank switching

Controller address contention assumption

Authenticating features of virtual server system

End-to-end protection for shrouded virtual servers

Instruction execution scheduling using a hit/miss predictor

Accuracy sensitive performance counters

Memory state indicator check operations

Memory state indicator check operations

Efficient generation of instrumentation data for direct memory access operations

Predictive scheduler for memory rank switching

Non-data inclusive coherent (NIC) directory for cache

Non-data inclusive coherent (NIC) directory for cache

Detecting and mitigating false structure sharing within a cache line

Method, system, and computer program product for pipeline arbitration

Accuracy sensitive performance counters

Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer

Controlling speculative actions based on a hit/miss predictor

Memory state indicator

Memory state indicator

Cleared memory indicator

Cleared memory indicator

Dynamic relocation of storage

Multilevel cache hierarchy for finding a cache line on a remote node

Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data

Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data

Authenticating features of virtual server system

End-to end protection for shrouded virtual servers

Lateral persistence directory states

Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications

Dual/multi-mode processor pipelines sampling

Dual/multi-mode processor pipeline sampling

Method for ensuring fairness among requests within a multi-node computer system

Concurrent modification of shared cache line by multiple processors

Conditional memory spreading for heterogeneous memory sizes

Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer

BLAKE MICHAEL A

Maintaining cache coherence in a multi-node, symmetric multiprocessing computer

Maintaining cache coherence in a multi-node, symmetric multiprocessing computer

Apparatus and method for improved data persistence within a multi-node system

DRAPALA GARRETT M

Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing system

Main memory operations in a symmetric multiprocessing computer

Controlling data stream interruptions on a shared interface

WHEELOCK INC

Method and apparatus for sending a weather condition alert

BRONSON TIMOTHY C

Multilevel cache hierarchy for finding a cache line on a remote node

HUTTON DAVID S

Method, system and computer program product for generalized LRU in cache and memory performance analysis and modeling