Inventor
NAIR RAJENDRAN
US33 patents
⚠️ This page may combine multiple inventors who share the name “NAIR RAJENDRAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS6529398B1Mar 4, 2003
Ferroelectric memory and method for reading the same
INTEL CORP76 citations96
US6448840B2Sep 10, 2002
Adaptive body biasing circuit and method
INTEL CORP63 citations94
US6351191B1Feb 26, 2002
Differential delay cell with common delay control and power supply
INTEL CORP45 citations93
US6304141B1Oct 16, 2001
Complementary input self-biased differential amplifier with gain compensation
INTEL CORP30 citations93
US6522568B1Feb 18, 2003
Ferroelectric memory and method for reading the same
INTEL CORP22 citations92
US6366320B1Apr 2, 2002
High speed readout architecture for analog storage arrays
INTEL CORP43 citations92
US6611448B2Aug 26, 2003
Ferroelectric memory and method for reading the same
INTEL CORP39 citations91
US6456133B1Sep 24, 2002
Duty cycle control loop
INTEL CORP21 citations88
US6664834B2Dec 16, 2003
Method for automatic duty cycle control using adaptive body bias control
INTEL CORP38 citations87
US6717445B1Apr 6, 2004
Symmetric voltage follower buffer
INTEL CORP14 citations84
US6538502B2Mar 25, 2003
High bandwidth switched capacitor input receiver
INTEL CORP17 citations84
US6411151B1Jun 25, 2002
Low jitter external clocking
INTEL CORP15 citations84
US6377108B1Apr 23, 2002
Low jitter differential amplifier with negative hysteresis
INTEL CORP15 citations84
US6229357B1May 8, 2001
Frequency divider and method
INTEL CORP15 citations84
US6208186B1Mar 27, 2001
Differential signal generator
INTEL CORP19 citations84
US6958632B2Oct 25, 2005
Symmetric voltage follower buffer
INTEL CORP9 citations74
US6828638B2Dec 7, 2004
Decoupling capacitors for thin gate oxides
INTEL CORP9 citations74
US6798265B2Sep 28, 2004
Low jitter external clocking
INTEL CORP10 citations73
US6420912B1Jul 16, 2002
Voltage to current converter
INTEL CORP9 citations71
US7405364B2Jul 29, 2008
Decoupled signal-power substrate architecture
INTEL CORP6 citations63
US6878572B2Apr 12, 2005
High capacitance package substrate
INTEL CORP3 citations63
US6849909B1Feb 1, 2005
Method and apparatus for weak inversion mode MOS decoupling capacitor
INTEL CORP4 citations63
US6552887B1Apr 22, 2003
Voltage dependent capacitor configuration for higher soft error rate tolerance
INTEL CORP4 citations63
US6466473B2Oct 15, 2002
Method and apparatus for increasing signal to sneak ratio in polarizable cross-point matrix memory arrays
INTEL CORP5 citations61
US6812757B2Nov 2, 2004
Phase lock loop apparatus
INTEL CORP2 citations60
US7053481B2May 30, 2006
High capacitance package substrate
INTEL CORP0 citations52
NAIR RAJENDRAN
6 patentsUS7449639B2Nov 11, 2008
Shielded flat pair cable architecture
NAIR RAJENDRAN15 citations92
US7126387B2Oct 24, 2006
Method and apparatus for driving low input impedance power transistor switches
NAIR RAJENDRAN23 citations92
US7378898B2May 27, 2008
Voltage droop suppressing circuit
NAIR RAJENDRAN9 citations84
US7348810B1Mar 25, 2008
Push pull high-swing capable differential signaling circuits
NAIR RAJENDRAN11 citations84
US8563865B2Oct 22, 2013
Flat wire shielded pair and cable
NAIR RAJENDRAN5 citations73
US7291896B2Nov 6, 2007
Voltage droop suppressing active interposer
NAIR RAJENDRAN5 citations62