Inventor

SHARPE-GEISLER BRADLEY A

US96 patents

⚠️ This page may combine multiple inventors who share the name “SHARPE-GEISLER BRADLEY A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHARPE-GEISLER BRADLEY A

VANTIS CORP

Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits

Efficient interconnect network for use in FPGA device having variable grain architecture

Synthesis-friendly FPGA architecture with variable length and variable timing interconnect

FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals

Band gap reference using a low voltage power supply

Variable grain architecture for FPGA integrated circuits

Methods for configuring FPGA&#39;s having variable grain components for providing time-shared access to interconnect resources

FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks

Tileable and compact layout for super variable grain blocks within FPGA device

Dual port SRAM memory for run time use in FPGA integrated circuits

Circuitry to provide fast carry

Clock tree topology

Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5 volt) semiconductor process

Semiconductor-oxide-semiconductor capacitor formed in integrated circuit

FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections

High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device

Electrostatic discharge (ESD) protection for a 5.0 volt compatible input/output (I/O) in a 2.5 volt semiconductor process

Enhanced I/O control flexibility for generating control signals

ADVANCED MICRO DEVICES INC

Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices

CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors

Memory bits used to couple look up table inputs to facilitate increased availability to routing resources particularly for variable sized look up tables for a field programmable gate array (FPGA)

Block clock and initialization circuit for a complex high density PLD

Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD

Field programmable gate array (FPGA) with interconnect encoding

Lock generator circuit for use with a dual edge register that provides a separate enable for each use of an input clock signal

CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase

Macrocell and clock signal allocation circuit for a programmable logic device (PLD) enabling PLD resources to provide multiple functions

Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation

Input buffer providing virtual hysteresis

Field programmable gate array (FPGA) having an improved configuration memory and look up table

Reference for CMOS memory cell having PMOS and NMOS transistors with a common floating gate

Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device

Capacitance elimination circuit which provides current to a node in a circuit to eliminate the effect of parasitic capacitance at the node

Ground bounce isolated output buffer

Latching zero-power sense amplifier with cascode

Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching

LATTICE SEMICONDUCTOR CORP

FPGA with register-intensive architecture

Variable grain architecture for FPGA integrated circuits

Methods for configuring FPGA&#39;s having variable grain components for providing time-shared access to interconnect resources

Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device

Input buffer with CMOS driver gate current control enabling selectable PCL, GTL, or PECL compatibility

Electrostatic discharge protection circuit

Band gap reference circuit

Output buffer having programmable drive current and output voltage limits

Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device

FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode

Programmable input/output block (IOB) in FPGA integrated circuits

Field programmable gate array having embedded memory with configurable depth and width

Variable grain architecture for FPGA integrated circuits

MONOLITHIC MEMORIES INC

Method for forming a fuse

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources