Inventor

IRELAND PHILIP J

US69 patents

⚠️ This page may combine multiple inventors who share the name “IRELAND PHILIP J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IRELAND PHILIP J

MICRON TECHNOLOGY INC

Passivation integrity improvements

Polysilicon pillar diode for use in a non-volatile memory cell

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

Capacitance reduction by tunnel formation for use with semiconductor device

Method of making a contact structure

Capacitance reduction by tunnel formation for use with a semiconductor device

Fill pattern generation for spin-on-glass and related self-planarization deposition

Contact structure for integrated circuit devices

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

Passivation integrity improvements

Process for forming trenches and contacts during the formation of a semiconductor memory device

Capacitor structures

Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon

Expanded implantation of contact holes

Apparatuses and methods for die seal crack detection

Apparatuses and methods for die seal crack detection

Self-aligned, integrated circuit contact

Design layout method for metal lines of an integrated circuit

Process for forming electrical interconnects in integrated circuits

Method of fabricating a sleeve insulator for a contact structure

Method of making a contact structure

Metal line layout of an integrated circuit

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

Subresolution features for a semiconductor device

Methods of forming conductive interconnects

Self-aligned, integrated circuit contact and formation method

Methods of forming conductive interconnects

Subresolution features for a semiconductor device

Chemistry for chemical vapor deposition of titanium containing films

Creation of subresolution features via flow characteristics

Photo-lithography process using multiple anti-reflective coatings

Semiconductor constructions having through-substrate interconnects

Contact formation using two anneal steps

Method and apparatus for a deposited fill layer

Trench interconnect structure and formation method

Self-aligned, integrated circuit contact

Photolithography process using multiple anti-reflective coatings

Capacitance reduction by tunnel formation for use with a semiconductor device

Trench interconnect structure and formation method

Chemistry for chemical vapor deposition of titanium containing films

Fill pattern generation for spin-on glass and related self-planarization deposition

Integrated circuit with modified metal features and method of fabrication therefor

Creation of subresolution features via flow characteristics

Fill pattern generation for spin-on glass and related self-planarization deposition

Passivation integrity improvements

Chemistry for chemical vapor deposition of titanium containing films

INTEL CORP

Electronic component guard ring

Electronic component guard ring

MICRON SEMICONDUCTOR INC

Double mask process for forming trenches and contacts during the formation of a semiconductor memory device

WOOD ALAN G

Methods of forming through-substrate interconnects