Inventor

SHARAN SUJIT

US199 patents

⚠️ This page may combine multiple inventors who share the name “SHARAN SUJIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHARAN SUJIT

MICRON TECHNOLOGY INC

Combined gate cap or digit line and spacer deposition using HDP

Quasi-remote plasma processing method and apparatus

Apparatus and method to increase gas residence time in a reactor

Low scratch density chemical mechanical planarization process

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor

Process of polishing a semiconductor wafer having an orientation edge discontinuity shape

Polishing apparatus, a polishing wafer carrier apparatus, a replacable component for a particular polishing apparatus and a process of polishing wafers

Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants

Plasma enhanced chemical vapor deposition reactor and plasma enhanced chemical vapor deposition process

Combined gate cap or digit line and spacer deposition using HDP

Method for PECVD deposition of selected material films

Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks

RF powered plasma enhanced chemical vapor deposition reactor and methods

Method of making a field effect transistor having an elevated source and an elevated drain

Method of forming a crystalline phase material

Method of forming titanium silicide and titanium by chemical vapor deposition

Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants

Removal of metal cusp for improved contact fill

Low cost DRAM metallization

Method of forming an electrical contact to a silicon substrate

Methods of forming a silicon nitrite film, a capacitor dielectric layer and a capacitor

Method of making a field effect transistor having an elevated source and an elevated drain

Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts

Method for forming low contact resistance contacts, vias, and plugs with diffusion barriers

Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants

Device for in-situ cleaning of an inductively-coupled plasma chambers

Semiconductor processing methods of forming an utilizing antireflective material layers, and methods of forming transistor gate stacks

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus

Plasma enhanced chemical vapor deposition process

Removal of metal cusp for improved contact fill

Capacitor structures

Process for making low dielectric constant dielectric films

Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon

Methods of forming a contact having titanium silicide and titanium formed by chemical vapor deposition

RF powered plasma enhanced chemical vapor deposition reactor and methods of effecting plasma enhanced chemical vapor deposition

RF powered plasma enhanced chemical vapor deposition reactor and methods

Apparatus having titanium silicide and titanium formed by chemical vapor deposition

Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants

Low dielectric constant dielectric films and process for making the same

Method of forming field emission devices

Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening

Method of forming an electrical contact to a silicon substrate

Method of increasing capacitance of memory cells incorporating hemispherical grained silicon

INTEL CORP

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages

Passive components in vias in a stacked integrated circuit package

Electrochemical mechanical planarization

BRAUNISCH HENNING

Multi-chip package and method of providing die-to-die interconnects in same

(unassigned)

Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor