Inventor

ANDREEV ALEXANDER

US40 patents

⚠️ This page may combine multiple inventors who share the name “ANDREEV ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDREEV ALEXANDER

LSI CORP

Memory timing model with back-annotating

Parallel LDPC decoder

Low complexity LDPC encoding algorithm

Density driven layout for RRAM configuration module

Multimode delay analysis for simplifying integrated circuit design timing models

Density driven layout for RRAM configuration module

Methods and apparatus for programmable decoding of a plurality of code types

Circuits for implementing parity computation in a parallel architecture LDPC decoder

Built in self test transport controller architecture

Decision tree representation of a function

High performance tiling for RRAM memory

Methods and apparatus for fast unbalanced pipeline architecture

Pipelined LDPC arithmetic unit

LSI LOGIC CORP

Metal layer assignment

Wire routing optimization

Method and apparatus for formula area and delay minimization

Method and apparatus for locating constants in combinational circuits

Method and apparatus for detecting equivalent and anti-equivalent pins

Method and apparatus for minimization of net delay by optimal buffer insertion

RRAM flipflop rcell memory generator

RRAM controller built in self test memory

RRAM backend flow

EASIC CORP

Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC

Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node

Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

Via-configurable high-performance logic block involving transistor chains

ACRONIS INT GMBH

Systems and methods for multiplexing data of an underlying index

Systems and methods for performing data migration between data centers

Systems and methods for improving indexer performance by multiplexing data of an underlying index

Systems and methods for providing nested frontend applications for managed service providers

ANDREEV ALEXANDER

Via-configurable high-performance logic block architecture

Configurable Reed-Solomon decoder based on modified Forney syndromes

Variable node processing unit

INTEL CORP

Configurable clock macro circuits and methods

Systems and methods for generating placements for circuit designs using pyramidal flows

Circuits and methods for routing crossbars with programmable vias

PANTELEEV PAVEL A

Scheme for erasure locator polynomial calculation in error-and-erasure decoder

LSICorporation

Low area architecture in BCH decoder

AVAGO TECHNOLOGIES GENERAL IP

Variable node processing unit

GRIBOK SERGEY

Cryptographic random number generator using finite field operations