Inventor

PAVISIC IVAN

US55 patents

⚠️ This page may combine multiple inventors who share the name “PAVISIC IVAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAVISIC IVAN

LSI LOGIC CORP

Advanced modular cell placement system

Metal layer assignment

Advanced modular cell placement system

Method and system for classifying an integrated circuit for optical proximity correction

Wire routing optimization

Method and apparatus for horizontal congestion removal

Method and apparatus for vertical congestion removal

Integrated circuit floor plan optimization system

Method in integrating clock tree synthesis and timing optimization for an integrated circuit design

Method and apparatus for congestion driven placement

Changing clock delays in an integrated circuit for skew optimization

Physical design automation system and process for designing integrated circuit chip using &#34;chessboard&#34; and &#34;jiggle&#34; optimization

Physical design automation system and process for designing integrated circuit chip using simulated annealing with &#34;chessboard and jiggle&#34; optimization

Optimizing IC clock structures by minimizing clock uncertainty

Clock tree synthesis with skew for memory devices

Assignment of cell coordinates

Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances

Distribution dependent clustering in buffer insertion of high fanout nets

Method and apparatus for parallel routing locking mechanism

Netlist resynthesis program using structure co-factoring

Compact custom layout for RRAM column controller

Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells

Netlist resynthesis program based on physical delay calculation

Optimizing IC clock structures by minimizing clock uncertainty

Timing-driven placement method utilizing novel interconnect delay model

Process of restructuring logics in ICs for setup and hold time optimization

Floor plan tester for integrated circuit design

Parallelization of resynthesis

Modifying timing graph to avoid given set of paths

Method and apparatus for determining wire routing

Method and apparatus for continuous column density optimization

Parallel processing of Integrated circuit pin arrival times

Efficient multiprocessing for cell placement of integrated circuits

Power routing with obstacles

System and method for identifying and eliminating bottlenecks in integrated circuit designs

Process for layout of memory matrices in integrated circuits

Process layout of buffer modules in integrated circuits

Timing recomputation

Chip core size estimation

IC timing analysis with known false paths

Integrated circuit cell placement parallelization with minimal number of conflicts

Optimal clock timing schedule for an integrated circuit

LSI CORP

Density driven layout for RRAM configuration module

Signal delay skew reduction system

Density driven layout for RRAM configuration module

Method of buffer insertion to achieve pin specific delays

NIKITIN ANDREY

Method and computer program for generating grounded shielding wires for signal wiring

Method and apparatus for balancing signal delay skew

LSI LOGIG CORP

Method and apparatus for congestion removal

EASIC CORP

Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization

Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization