Inventor
RASPOPOVIC PEDJA
US20 patents
⚠️ This page may combine multiple inventors who share the name “RASPOPOVIC PEDJA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
18 patentsUS6324674B2Nov 27, 2001
Method and apparatus for parallel simultaneous global and detail routing
LSI LOGIC CORP206 citations99
US6289495B1Sep 11, 2001
Method and apparatus for local optimization of the global routing
LSI LOGIC CORP166 citations99
US6253363B1Jun 26, 2001
Net routing using basis element decomposition
LSI LOGIC CORP153 citations99
US6182272B1Jan 30, 2001
Metal layer assignment
LSI LOGIC CORP332 citations99
US6175950B1Jan 16, 2001
Method and apparatus for hierarchical global routing descend
LSI LOGIC CORP157 citations99
US6412102B1Jun 25, 2002
Wire routing optimization
LSI LOGIC CORP139 citations98
US6247167B1Jun 12, 2001
Method and apparatus for parallel Steiner tree routing
LSI LOGIC CORP131 citations98
US6230306B1May 8, 2001
Method and apparatus for minimization of process defects while routing
LSI LOGIC CORP148 citations98
US6154874ANov 28, 2000
Memory-saving method and apparatus for partitioning high fanout nets
LSI LOGIC CORP91 citations98
US6260183B1Jul 10, 2001
Method and apparatus for coarse global routing
LSI LOGIC CORP58 citations96
US6269469B1Jul 31, 2001
Method and apparatus for parallel routing locking mechanism
LSI LOGIC CORP25 citations92
US7020589B1Mar 28, 2006
Method and apparatus for adaptive timing optimization of an integrated circuit design
LSI LOGIC CORP33 citations89
US6546539B1Apr 8, 2003
Netlist resynthesis program using structure co-factoring
LSI LOGIC CORP39 citations89
US6643832B1Nov 4, 2003
Virtual tree-based netlist model and method of delay estimation for an integrated circuit design
LSI LOGIC CORP30 citations88
US6557144B1Apr 29, 2003
Netlist resynthesis program based on physical delay calculation
LSI LOGIC CORP16 citations84
US6505336B1Jan 7, 2003
Channel router with buffer insertion
LSI LOGIC CORP10 citations74
US6463572B1Oct 8, 2002
IC timing analysis with known false paths
LSI LOGIC CORP5 citations63
US6453453B1Sep 17, 2002
Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes
LSI LOGIC CORP3 citations63