Inventor

LUKANC TODD P

US44 patents

⚠️ This page may combine multiple inventors who share the name “LUKANC TODD P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUKANC TODD P

ADVANCED MICRO DEVICES INC

Optimized trench/via profile for damascene processing

Optimized trench/via profile for damascene filling

Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results

Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film

Method for using a CVD organic barc as a hard mask during via etch

Optimized trench/via profile for damascene filling

System and method for design rule creation and selection

Method and apparatus for generating trenches for vias

Optimizing dense via arrays of shrunk integrated circuit designs

Multilayer anti-reflective coating process for integrated circuit fabrication

Bright field image reversal for contact hole patterning

Optimized trench/via profile for damascene filling

Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

Method for fabricating protected copper metallization

Method of lithographic image alignment for use with a dual mask exposure technique

Two mask photoresist exposure pattern for dense and isolated regions

Slotted trench dual inlaid structure and method of forming thereof

Reduce line end pull back by exposing and etching space after mask one trim and etch

Two mask photoresist exposure pattern for dense and isolated regions

Method and enhancing clear field phase shift masks with border around edges of phase regions

Method of enhancing gate patterning properties with reflective hard mask

Method of enhancing clear field phase shift masks with chrome border around phase 180 regions

Process for etching an organic dielectric using a silyated photoresist mask

Method and apparatus for determining an etch endpoint

Connection structures for integrated circuits and processes for their formation

Sidewall spacer definition of gates

Dark field image reversal for gate or line patterning

Conductive material adhesion enhancement in damascene process for semiconductors

Method of providing a frontside contact to substrate of SOI device

Lithographic photomask and method of manufacture to improve photomask test measurement

Self-aligned conductive plugs in a semiconductor device

Method of enhancing clear field phase shift masks with border regions around phase 0 and phase 180 regions

Process for forming a photoresist mask

Method of enhancing clear field phase shift masks by adding parallel line to phase 0 region

Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer

System and method for designing an integrated circuit device

Predefined critical spaces in IC patterning to reduce line end pull back

Device and method for determining an illumination intensity profile of an illuminator for a lithography system

Method of extending the areas of clear field phase shift generation

Microdevice having non-linear structural component and method of fabrication

Method of providing a frontside contact to a substrate of SOI device

GLOBALFOUNDRIES INC

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

Methods and systems for designing and manufacturing optical lithography masks