Inventor

MCLAURY LOREN L

US53 patents

⚠️ This page may combine multiple inventors who share the name “MCLAURY LOREN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCLAURY LOREN L

MICRON TECHNOLOGY INC

Fast, low power, write scheme for memory circuits using pulsed off isolation device

Data transfer circuit in a memory device

Method and apparatus for multiple latency synchronous pipelined dynamic random access memory

Dynamic memory with isolated digit lines

Multiport memory with pipelined serial input

Multiple register block write method and circuit for video DRAMs

Method and apparatus for multiple latency synchronous dynamic random access memory

Method and apparatus for multiple latency synchronous dynamic random access memory

Method for multiple latency synchronous dynamic random access memory

Power up intialization circuit responding to an input signal

Dual strobed negative pumped wordlines for dynamic random access memories

Pipelined SAM register serial output

Dual strobed negative pumped worldlines for dynamic random access memories

Fast, low power, write scheme for memory circuits using pulsed off isolation device

Enhanced multiple block writes to adjacent blocks of memory using a sequential counter

Single ended transfer circuit

Equilibrated sam read transfer circuit

Multiport memory with pipelined serial input

Single P-sense AMP circuit using depletion isolation devices

True tristate output buffer and a method for driving a potential of an output pad to three distinct conditions

Integrated circuit memory with asymmetric row access topology

Integrated circuit memory with isolation of column line portions through P-sense amplification period

DRAM with a two stage voltage pull-down sense amplifier

MOSFET gate substrate bias sensor

Method and apparatus for multiple latency synchronous dynamic random access memory

Method and apparatus for multiple latency synchronous dynamic random access memory

Power up initialization circuit responding to an input signal

Method and apparatus for multiple latency synchronous dynamic random access memory

Power up initialization circuit responding to an input signal

Power up initialization circuit responding to an input signal

Fast, low power, write scheme for memory circuits using pulsed off isolation device

Power up initialization circuit responding to an input signal

Enhanced multiple block writes to adjacent block of memory using a sequential counter

Multi-bit block write in a random access memory

Multi-port memory with multiple function access cycles and transfers with simultaneous random access

Page mode editable real time read transfer

Multi-bit block write in a random access memory

Circuit and method for externally controlling signal development in a serial access memory

Fast, low power, write scheme for memory circuits using pulsed off isolation device

Multi-bit block write in a random access memory

VRAM having isolated array sections for providing write functions that will not affect other array sections

MICRON SEMICONDUCTOR INC

Memory with isolated digit lines

Row decoder/driver circuit for determining non selected wordlines and for driving non-selected wordlines to a potential less than the lowest potential of the digit lines

Pumped wordlines

VRAM having isolated array sections for providing write functions that will not affect other array sections

LATTICE SEMICONDUCTOR CORP

Memory access circuit and method for reading and writing data with the same clock signal

Dual power supplied memory cells and deterministic reset thereof for programmable logic devices

Selectively powered embedded memory systems and methods

Negative voltage blocking for embedded memories

MICRON TECHNOLOGIES INC

Integrated circuit memory with dual P-sense amplifiers associated with each column line