Inventor
BUDNAITIS JOHN J
US12 patents
⚠️ This page may combine multiple inventors who share the name “BUDNAITIS JOHN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GORE & ASS
11 patentsUS5896038AApr 20, 1999
Method of wafer level burn-in
GORE & ASS169 citations97
US5886535AMar 23, 1999
Wafer level burn-in base unit substrate and assembly
GORE & ASS109 citations97
US5766979AJun 16, 1998
Wafer level contact sheet and method of assembly
GORE & ASS99 citations97
US6313411B1Nov 6, 2001
Wafer level contact sheet and method of assembly
GORE & ASS30 citations92
US6046060AApr 4, 2000
Method of making a high planarity, low CTE base for semiconductor reliability screening
GORE & ASS29 citations92
US6011697AJan 4, 2000
Constraining ring for use in electronic packaging
GORE & ASS43 citations92
US5909123AJun 1, 1999
Method for performing reliability screening and burn-in of semi-conductor wafers
GORE & ASS32 citations92
US5830565ANov 3, 1998
High planarity and low thermal coefficient of expansion base for semi-conductor reliability screening
GORE & ASS26 citations92
US5966022AOct 12, 1999
Wafer level burn-in system
GORE & ASS35 citations91
US5966593AOct 12, 1999
Method of forming a wafer level contact sheet having a permanent z-axis material
GORE & ASS39 citations91
US5879786AMar 9, 1999
Constraining ring for use in electronic packaging
GORE & ASS11 citations73