Inventor
LAYADI NACE
US26 patents
⚠️ This page may combine multiple inventors who share the name “LAYADI NACE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AGERE SYSTEMS INC
10 patentsUS6910907B2Jun 28, 2005
Contact for use in an integrated circuit and a method of manufacture therefor
AGERE SYSTEMS INC115 citations98
US6576529B1Jun 10, 2003
Method of forming an alignment feature in or on a multilayered semiconductor structure
AGERE SYSTEMS INC14 citations91
US6720604B1Apr 13, 2004
Capacitor for an integrated circuit
AGERE SYSTEMS INC16 citations83
US6727588B1Apr 27, 2004
Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
AGERE SYSTEMS INC15 citations79
US6977128B2Dec 20, 2005
Multi-layered semiconductor structure
AGERE SYSTEMS INC9 citations72
US6656850B2Dec 2, 2003
Method for in-situ removal of side walls in MOM capacitor formation
AGERE SYSTEMS INC7 citations72
US6730600B2May 4, 2004
Method of dry etching a semiconductor device in the absence of a plasma
AGERE SYSTEMS INC6 citations63
US6548906B2Apr 15, 2003
Method for reducing a metal seam in an interconnect structure and a device manufactured thereby
AGERE SYSTEMS INC2 citations63
US6706609B2Mar 16, 2004
Method of forming an alignment feature in or on a multi-layered semiconductor structure
AGERE SYSTEMS INC4 citations61
US6585830B2Jul 1, 2003
Method for cleaning tungsten from deposition wall chambers
AGERE SYSTEMS INC1 citations52
AGERE SYST GUARDIAN CORP
10 patentsUS6218255B1Apr 17, 2001
Method of making a capacitor
AGERE SYST GUARDIAN CORP18 citations92
US6258610B1Jul 10, 2001
Method analyzing a semiconductor surface using line width metrology with auto-correlation operation
AGERE SYST GUARDIAN CORP45 citations90
US6436829B1Aug 20, 2002
Two phase chemical/mechanical polishing process for tungsten layers
AGERE SYST GUARDIAN CORP16 citations84
US6406999B1Jun 18, 2002
Semiconductor device having reduced line width variations between tightly spaced and isolated features
AGERE SYST GUARDIAN CORP17 citations81
US6395639B1May 28, 2002
Process for improving line width variations between tightly spaced and isolated features in integrated circuits
AGERE SYST GUARDIAN CORP15 citations81
US6358790B1Mar 19, 2002
Method of making a capacitor
AGERE SYST GUARDIAN CORP8 citations73
US6249016B1Jun 19, 2001
Integrated circuit capacitor including tapered plug
AGERE SYST GUARDIAN CORP11 citations73
US6458648B1Oct 1, 2002
Method for in-situ removal of side walls in MOM capacitor formation
AGERE SYST GUARDIAN CORP10 citations72
US6472307B1Oct 29, 2002
Methods for improved encapsulation of thick metal features in integrated circuit fabrication
AGERE SYST GUARDIAN CORP10 citations71
US6323537B1Nov 27, 2001
Capacitor for an integrated circuit
AGERE SYST GUARDIAN CORP4 citations62
LUCENT TECHNOLOGIES INC
3 patentsUS6180518B1Jan 30, 2001
Method for forming vias in a low dielectric constant material
LUCENT TECHNOLOGIES INC100 citations98
US6204186B1Mar 20, 2001
Method of making integrated circuit capacitor including tapered plug
LUCENT TECHNOLOGIES INC20 citations92
US6218085B1Apr 17, 2001
Process for photoresist rework to avoid sodium incorporation
LUCENT TECHNOLOGIES INC14 citations69
CHARTERED SEMICONDUCTOR MFG
3 patentsUS6984166B2Jan 10, 2006
Zone polishing using variable slurry solid content
CHARTERED SEMICONDUCTOR MFG35 citations89
US6821886B1Nov 23, 2004
IMP TiN barrier metal process
CHARTERED SEMICONDUCTOR MFG19 citations82
US7163438B2Jan 16, 2007
Zone polishing using variable slurry solid content
CHARTERED SEMICONDUCTOR MFG2 citations59