Inventor

HA CHANG WAN

US73 patents

⚠️ This page may combine multiple inventors who share the name “HA CHANG WAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HA CHANG WAN

MICRON TECHNOLOGY INC

Program method with optimized voltage level for flash memory

Program method with optimized voltage level for flash memory

Semiconductor devices including stair step structures, and related methods

Charge pump operation in a non-volatile memory device

Interleaved input signal path for multiplexed input

Stair step formation using at least two masks

Power management

Methods of operating a memory device

Stair step formation using at least two masks

Dynamic data caches, decoders and decoding methods

Semiconductor devices including stair step structures, and related methods

Dynamic data caches, decoders and decoding methods

Stair step formation using at least two masks

Sub-block decoding in 3D memory

Method for reading a multilevel cell in a non-volatile memory device

Program and sense operations in a non-volatile memory device

Method for reading a multilevel cell in a non-volatile memory device

Memory cell repair using fuse programming method in a flash memory device

Power management

Controlling a memory device responsive to degradation

Program method with optimized voltage level for flash memory

NAND memory device and programming methods

Memory cell repair using fuse programming method in a flash memory device

Noise suppression in memory device sensing

Devices including stair step structures, and related apparatuses and memory devices

Testing impedance adjustment

Sub-block disabling in 3D memory

Method for reading a multilevel cell in a non-volatile memory device

Charge pump operation in a non-volatile memory device

NAND memory device and programming methods

Program method with optimized voltage level for flash memory

Noise suppression in memory device sensing

Layout for NAND flash memory array having reduced word line impedance

HA CHANG WAN

Stair step formation using at least two masks

Controlling a memory device responsive to degradation

Dynamic data caches, decoders and decoding methods

Apparatuses and methods for operating a memory device

Charge pump operation in a non-volatile memory device

WINBOND ELECTRONICS CORP

Flash memory having a flexible bank partition

Column decoder with increased immunity to high voltage breakdown

Semiconductor memory having a flexible dual-bank architecture with improved row decoding

Memory architecture with vertical and horizontal row decoding

Source biasing circuit for flash EEPROM

HYUNDAI ELECTRONICS IND

Circuit of sensing a fuse cell in a flash memory

Repair fuse circuit in a flash memory device

Flash memory device using an operational circuit for bit-by-bit verifying of programmed data in memory cells and method of programming the same

INTEL CORP

Defective bit line management in connection with a memory access

Program verification time reduction in non-volatile memory devices

Defective bit line management in connection with a memory access

SK HYNIX INC

Memory device, memory system including the same and operation method of the memory system