Inventor
HUM HERBERT
US27 patents
⚠️ This page may combine multiple inventors who share the name “HUM HERBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
22 patentsUS9829965B2Nov 28, 2017
Distribution of tasks among asymmetric processing elements
INTEL CORP11 citations92
US7095342B1Aug 22, 2006
Compressing microcode
INTEL CORP19 citations92
US6798364B2Sep 28, 2004
Method and apparatus for variable length coding
INTEL CORP37 citations92
US11054890B2Jul 6, 2021
Distribution of tasks among asymmetric processing elements
INTEL CORP3 citations84
US9874926B2Jan 23, 2018
Distribution of tasks among asymmetric processing elements
INTEL CORP2 citations84
US9870046B2Jan 16, 2018
Distribution of tasks among asymmetric processing elements
INTEL CORP2 citations84
US9760162B2Sep 12, 2017
Distribution of tasks among asymmetric processing elements
INTEL CORP3 citations84
US9753530B2Sep 5, 2017
Distribution of tasks among asymmetric processing elements
INTEL CORP3 citations84
US6954822B2Oct 11, 2005
Techniques to map cache data to memory arrays
INTEL CORP18 citations84
US7958336B2Jun 7, 2011
System and method for reservation station load dependency matrix
INTEL CORP17 citations83
US7054999B2May 30, 2006
High speed DRAM cache architecture
INTEL CORP7 citations74
US11366511B2Jun 21, 2022
Distribution of tasks among asymmetric processing elements
INTEL CORP0 citations62
US9939882B2Apr 10, 2018
Systems and methods for migrating processes among asymmetrical processing cores
INTEL CORP1 citations62
US9910483B2Mar 6, 2018
Distribution of tasks among asymmetric processing elements
INTEL CORP1 citations62
US7506108B2Mar 17, 2009
Requester-generated forward for late conflicts in a cache coherency protocol
INTEL CORP4 citations62
US10437320B2Oct 8, 2019
Distribution of tasks among asymmetric processing elements
INTEL CORP0 citations52
US10409360B2Sep 10, 2019
Distribution of tasks among asymmetric processing elements
INTEL CORP0 citations52
US10386915B2Aug 20, 2019
Distribution of tasks among asymmetric processing elements
INTEL CORP0 citations52
US7350016B2Mar 25, 2008
High speed DRAM cache architecture
INTEL CORP1 citations52
US9710391B2Jul 18, 2017
Methods and apparatuses for efficient load processing using buffers
INTEL CORP0 citations51
US10248568B2Apr 2, 2019
Efficient data transfer between a processor core and an accelerator
INTEL CORP0 citations44
US9880935B2Jan 30, 2018
Efficient data transfer between a processor core and an accelerator
INTEL CORP0 citations44
HUM HERBERT
2 patentsUS8615647B2Dec 24, 2013
Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state
HUM HERBERT34 citations94
US8151096B2Apr 3, 2012
Method to improve branch prediction latency
HUM HERBERT5 citations60