Inventor
PRUDVI CHINNA
US12 patents
⚠️ This page may combine multiple inventors who share the name “PRUDVI CHINNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
11 patentsUS6216208B1Apr 10, 2001
Prefetch queue responsive to read request sequences
INTEL CORP39 citations92
US6078981AJun 20, 2000
Transaction stall technique to prevent livelock in multiple-processor systems
INTEL CORP33 citations92
US6434677B1Aug 13, 2002
Method and apparatus for altering data length to zero to maintain cache coherency
INTEL CORP15 citations91
US6378048B1Apr 23, 2002
“SLIME” cache coherency system for agents with multi-layer caches
INTEL CORP29 citations91
US6401172B1Jun 4, 2002
Recycle mechanism for a processing agent
INTEL CORP6 citations73
US6209068B1Mar 27, 2001
Read line buffer and signaling protocol for processor
INTEL CORP12 citations73
US6735675B2May 11, 2004
Method and apparatus for altering data length to zero to maintain cache coherency
INTEL CORP10 citations72
US6578114B2Jun 10, 2003
Method and apparatus for altering data length to zero to maintain cache coherency
INTEL CORP9 citations72
US6412091B2Jun 25, 2002
Error correction system in a processing agent having minimal delay
INTEL CORP3 citations62
US6269465B1Jul 31, 2001
Error correction system in a processing agent having minimal delay
INTEL CORP2 citations62
US7555603B1Jun 30, 2009
Transaction manager and cache for processing agent
INTEL CORP1 citations51