Inventor

AIPPERSPACH ANTHONY GUS

US40 patents

Patents

40 patents

US6181614B1Jan 30, 2001

Lower power and reduced device split local and continuous bitline for domino read SRAMs

IBM21 citations92

US6833737B2Dec 21, 2004

SOI sense amplifier method and apparatus

IBM30 citations92

US6657886B1Dec 2, 2003

Split local and continuous bitline for fast domino read SRAM

IBM52 citations92

US6205063B1Mar 20, 2001

Apparatus and method for efficiently correcting defects in memory circuits

IBM38 citations92

US6172531B1Jan 9, 2001

Low power wordline decoder circuit with minimized hold time

IBM33 citations92

US6060909AMay 9, 2000

Compound domino logic circuit including an output driver section with a latch

IBM24 citations92

US6643804B1Nov 4, 2003

Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test

IBM37 citations91

US5991224ANov 23, 1999

Global wire management apparatus and method for a multiple-port random access memory

IBM33 citations91

US6737685B2May 18, 2004

Compact SRAM cell layout for implementing one-port or two-port operation

IBM21 citations86

US7161390B2Jan 9, 2007

Dynamic latching logic structure with static interfaces for implementing improved data setup time

IBM15 citations84

US6635518B2Oct 21, 2003

SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies

IBM15 citations84

US7528646B2May 5, 2009

Electrically programmable fuse sense circuit

IBM14 citations83

US7725844B2May 25, 2010

Method and circuit for implementing eFuse sense amplifier verification

IBM10 citations82

US7092281B1Aug 15, 2006

Method and apparatus for reducing soft error rate in SRAM arrays using elevated SRAM voltage during periods of low activity

IBM9 citations74

US6570433B2May 27, 2003

Laser fuseblow protection method for silicon on insulator (SOI) transistors

IBM5 citations74

US6509236B1Jan 21, 2003

Laser fuseblow protection method for silicon on insulator (SOI) transistors

IBM6 citations74

US7489572B2Feb 10, 2009

Method for implementing eFuse sense amplifier testing without blowing the eFuse

IBM6 citations73

US6404686B1Jun 11, 2002

High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus

IBM9 citations73

US6260164B1Jul 10, 2001

SRAM that can be clocked on either clock phase

IBM10 citations73

US6275427B1Aug 14, 2001

Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test

IBM11 citations72

US5991208ANov 23, 1999

Write multiplexer apparatus and method for multiple write port programmable memory

IBM12 citations72

US5835502ANov 10, 1998

Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme

IBM14 citations71

US7242233B2Jul 10, 2007

Simplified method for limiting clock pulse width

IBM2 citations63

US7689950B2Mar 30, 2010

Implementing Efuse sense amplifier testing without blowing the Efuse

IBM3 citations62

US7532057B2May 12, 2009

Electrically programmable fuse sense circuit

IBM4 citations62

US7289370B2Oct 30, 2007

Methods and apparatus for accessing memory

IBM6 citations62

US6247166B1Jun 12, 2001

Method and apparatus for assembling array and datapath macros

IBM4 citations62

US7764531B2Jul 27, 2010

Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor

IBM5 citations61

US7729188B2Jun 1, 2010

Method and circuit for implementing enhanced eFuse sense circuit

IBM5 citations60

US7400550B2Jul 15, 2008

Delay mechanism for unbalanced read/write paths in domino SRAM arrays

IBM2 citations60

US7206236B1Apr 17, 2007

Array redundancy supporting multiple independent repairs

IBM2 citations59

US7318209B2Jan 8, 2008

Pulse-width limited chip clock design

IBM1 citations52

US6661726B2Dec 9, 2003

Multiple mode elastic data transfer interface

IBM1 citations52

US7733722B2Jun 8, 2010

Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse

IBM1 citations51

US7535750B2May 19, 2009

Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells

IBM0 citations50

AIPPERSPACH ANTHONY GUS

Patents

Dynamic repair of redundant memory array

Multi-threaded cell for a memory

Master-slave latch circuit for multithreaded processing

Method and ring oscillator for evaluating dynamic circuits

Method and apparatus to reduce bias temperature instability (BTI) effects

Lower power and reduced device split local and continuous bitline for domino read SRAMs

SOI sense amplifier method and apparatus

Split local and continuous bitline for fast domino read SRAM

Apparatus and method for efficiently correcting defects in memory circuits

Low power wordline decoder circuit with minimized hold time

Compound domino logic circuit including an output driver section with a latch

Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test

Global wire management apparatus and method for a multiple-port random access memory

Compact SRAM cell layout for implementing one-port or two-port operation

Dynamic latching logic structure with static interfaces for implementing improved data setup time

SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies

Electrically programmable fuse sense circuit

Method and circuit for implementing eFuse sense amplifier verification

Method and apparatus for reducing soft error rate in SRAM arrays using elevated SRAM voltage during periods of low activity

Laser fuseblow protection method for silicon on insulator (SOI) transistors

Laser fuseblow protection method for silicon on insulator (SOI) transistors

Method for implementing eFuse sense amplifier testing without blowing the eFuse

High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus

SRAM that can be clocked on either clock phase

Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test

Write multiplexer apparatus and method for multiple write port programmable memory

Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme

Simplified method for limiting clock pulse width

Implementing Efuse sense amplifier testing without blowing the Efuse

Electrically programmable fuse sense circuit

Methods and apparatus for accessing memory

Method and apparatus for assembling array and datapath macros

Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor

Method and circuit for implementing enhanced eFuse sense circuit

Delay mechanism for unbalanced read/write paths in domino SRAM arrays

Array redundancy supporting multiple independent repairs

Pulse-width limited chip clock design

Multiple mode elastic data transfer interface

Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse

Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells