Inventor

BEHRENDS DERICK GARDNER

US19 patents

⚠️ This page may combine multiple inventors who share the name “BEHRENDS DERICK GARDNER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BEHRENDS DERICK GARDNER

IBM

Implementing boosted wordline voltage in memories

Method for implementing level shifter circuits for integrated circuits

Method for implementing SRAM cell write performance evaluation

Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare

Low power level shifting latch circuits with gated feedback for high speed integrated circuits

Flood mode implementation for continuous bitline local evaluation circuit

Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation

Apparatus for implementing SRAM cell write performance evaluation

Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels

Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability

Method for reducing wiring and required number of redundant elements

High performance read bypass test for SRAM circuits

Delay mechanism for unbalanced read/write paths in domino SRAM arrays

Multiple mode elastic data transfer interface

Flood mode implementation for continuous bitline local evaluation circuit

Maskable dynamic logic

BEHRENDS DERICK GARDNER

Delay chain burn-in for increased repeatability of physically unclonable functions

Data security for dynamic random access memory using body bias to clear data at power-up

Layout to minimize FET variation in small dimension photolithography