Inventor

JACOBSON HANS M

US63 patents

⚠️ This page may combine multiple inventors who share the name “JACOBSON HANS M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JACOBSON HANS M

IBM

Interlocked synchronous pipeline clock gating

Interlocked synchronous pipeline clock gating

Synchronous pipeline with normally transparent pipeline stages

Method and structure for short range leakage control in pipelined circuits

Processor with demand-driven clock throttling power reduction

Local bypass in memory computing

Low latency data exchange

Address generation in an active memory device

Interlocked synchronous pipeline clock gating

System and method for topology selection to minimize leakage power during synthesis

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

Method of stalling one or more stages in an interlocked synchronous pipeline

Active memory device gather, scatter, and filter

Clustering execution in a processing system to increase power savings

On-chip traffic prioritization in memory

Power management for in-memory computer systems

Power management for multi-core processing systems

Low-power circuit structures and methods for content addressable memories and random access memories

Circuit structures and methods for high-speed low-power select arbitration

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

On-chip traffic prioritization in memory

Clustering execution in a processing system to increase power savings

High bandwidth low latency data exchange between processing elements

High bandwidth low latency data exchange between processing elements

On-chip traffic prioritization in memory

Delaying execution in a processor to increase power savings

Delaying execution in a processor to increase power savings

Delaying execution in a processor to increase power savings

Chaining between exposed vector pipelines

Local bypass for in memory computing

Dynamic hard error detection

Dynamic power distribution

Power management for a computer system

Dynamic power distribution

Dynamic hard error detection

Low latency data exchange

Chaining between exposed vector pipelines

Power management for a computer system

Power-constrained compiler code generation and scheduling of work in a heterogeneous processing system

Power-constrained compiler code generation and scheduling of work in a heterogeneous processing system

Main processor support of tasks performed in memory

Main processor support of tasks performed in memory

FLEISCHER BRUCE M

Predication in a vector processor

Predication in a vector processor

Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry

Vector register file

Vector register file

JACOBSON HANS M

Task assignment on heterogeneous three-dimensional/stacked microarchitectures

Wave pipeline with selectively opaque register stages

BOSE PRADIP

Voltage regulator module with power gating and bypass