Inventor

CHANG LELAND

US138 patents

⚠️ This page may combine multiple inventors who share the name “CHANG LELAND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG LELAND

IBM

Integrated circuit having gates and active regions forming a regular grating

Integrated circuit having gates and active regions forming a regular grating

Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors

Selective floating body SRAM cell

Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance

Memory cell having improved read stability

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Back-gated fully depleted SOI transistor

Static random access memory utilizing gated diode technology

Sense amplifier circuits and high speed latch circuits using gated diodes

Fully integrated multi-phase buck converter with coupled air core inductors

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Hybrid CMOS nanowire mesh device and FINFET device

Method of fabricating MEMS transistors on far back end of line

Complementary SOI lateral bipolar for SRAM in a CMOS platform

Nanowire FET and FinFET hybrid technology

Double gate planar field effect transistors

Selective floating body SRAM cell

Embedded silicon germanium n-type filed effect transistor for reduced floating body effect

Dual dielectric tri-gate field effect transistor

Static random access memory (SRAM) cells

Method and structure for SOI body contact FET with reduced parasitic capacitance

High performance metal gate polygate 8 transistor SRAM cell with reduced variability

Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same

CHANG LELAND

Content addressable memory array programmed to perform logic operations

Time division multiplexed limited switch dynamic logic

Slab inductor device providing efficient on-chip supply voltage conversion and regulation

Electronic synapses for reinforcement learning

Sense scheme for phase change material content addressable memory

Low voltage signaling

Bi-directional self-aligned FET capacitor

Test structure for characterizing multi-port static random access memory and register file arrays

Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance

Asymmetric silicon-on-insulator SRAM cell

Contact scheme for FINFET structures with multiple FINs

CHANG JOSEPHINE B

Hybrid CMOS nanowire mesh device and FINFET device

Bulk FinFET and SOI FinFET hybrid technology

Multiple Vt field-effect transistor devices

Hybrid CMOS nanowire mesh device and PDSOI device

Double gate planar field effect transistors

Asymmetric finFET device with improved parasitic resistance and capacitance

Multiple Vt field-effect transistor devices

BANGSARUNTIP SARUNYA

Nanowire FET and finFET hybrid technology

Hybrid CMOS technology with nanowire devices and double gated planar devices

Hybrid CMOS technology with nanowire devices and double gated planar devices

UNIV CALIFORNIA

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

BREZZO BERNARD V

Reconfigurable and customizable general-purpose circuits for neural networks

GLOBALFOUNDRIES INC

Electronic device including moat power metallization in trench

SLEIGHT JEFFREY W

Body-tied asymmetric N-type field effect transistor