Inventor

LIN CHUNG-HSUN

US154 patents

⚠️ This page may combine multiple inventors who share the name “LIN CHUNG-HSUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN CHUNG-HSUN

IBM

Asymmetric high-k dielectric for reducing gate induced drain leakage

Diode structure and method for FINFET technologies

Recessed contact for multi-gate FET optimizing series resistance

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Graphene sensor

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Chemoepitaxy etch trim using a self aligned hard mask for metal line to via

Hybrid CMOS nanowire mesh device and FINFET device

Diode structure and method for wire-last nanomesh technologies

Diode structure and method for wire-last nanomesh technologies

Diode structure and method for gate all around silicon nanowire technologies

Diode structure for gate all around silicon nanowire technologies

FinFET devices containing merged epitaxial Fin-containing contact regions

Double gate planar field effect transistors

CHANG JOSEPHINE B

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Hybrid CMOS nanowire mesh device and FINFET device

Nanowire FET and finFET

Bulk FinFET and SOI FinFET hybrid technology

Hybrid CMOS nanowire mesh device and PDSOI device

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices

Double gate planar field effect transistors

Asymmetric finFET device with improved parasitic resistance and capacitance

Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure

Nanowire efuses

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices

Non-planar MOSFET structures with asymmetric recessed source drains and methods for making the same

BASKER VEERARAGHAVAN S

Method for fabricating finFET with merged fins and vertical silicide

finFET with merged fins and vertical silicide

GLOBALFOUNDRIES INC

Electronic device including moat power metallization in trench

Increased contact area for FinFETs

GUO DECHAO

Graphene sensor

Field effect transistor device and fabrication

TOSHIBA KK

Faceted EPI shape and half-wrap around silicide in S/D merged FinFET

BANGSARUNTIP SARUNYA

Epitaxially thickened doped or undoped core nanowire FET structure and method for increasing effective device width

CAI MING

Fin field effect transistor with variable channel thickness for threshold voltage tuning

(unassigned)

Baby-carrying bag

SLEIGHT JEFFREY W

Body-tied asymmetric N-type field effect transistor

ANDO TAKASHI

Source-drain extension formation in replacement metal gate transistor device