Inventor
LO SHIH-HSIEN
US12 patents
⚠️ This page may combine multiple inventors who share the name “LO SHIH-HSIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
7 patentsUS7342287B2Mar 11, 2008
Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures
IBM17 citations83
US8381156B1Feb 19, 2013
3D inter-stratum connectivity robustness
IBM8 citations82
US7274217B2Sep 25, 2007
High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs
IBM15 citations79
US8835191B2Sep 16, 2014
Nanowire stress sensors and stress sensor integrated circuits, design structures for a stress sensor integrated circuit, and related methods
IBM4 citations73
US9087909B2Jul 21, 2015
Hybrid extremely thin silicon-on-insulator (ETSOI) structure to minimize noise coupling from TSV
IBM1 citations62
US10083880B2Sep 25, 2018
Hybrid ETSOI structure to minimize noise coupling from TSV
IBM0 citations51
US9653615B2May 16, 2017
Hybrid ETSOI structure to minimize noise coupling from TSV
IBM0 citations51
BANSAL ADITYA
2 patentsUS8139400B2Mar 20, 2012
Enhanced static random access memory stability using asymmetric access transistors and design structure for same
BANSAL ADITYA7 citations83
US8526219B2Sep 3, 2013
Enhanced static random access memory stability using asymmetric access transistors and design structure for same
BANSAL ADITYA0 citations51