Inventor
PINEDA DE GYVEZ JOSE DE JESUS
NL32 patents
⚠️ This page may combine multiple inventors who share the name “PINEDA DE GYVEZ JOSE DE JESUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NXP BV
23 patentsUS7619431B2Nov 17, 2009
High sensitivity magnetic built-in current sensor
NXP BV115 citations95
US10270448B1Apr 23, 2019
Level shifter circuit with transistor drive strength variation compensation
NXP BV16 citations82
US7577858B2Aug 18, 2009
Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device
NXP BV13 citations82
US9678564B2Jun 13, 2017
Multiprocessor system with interrupt distributor
NXP BV8 citations81
US7200057B2Apr 3, 2007
Test for weak SRAM cells
NXP BV15 citations81
US7500204B2Mar 3, 2009
Real-time adaptive control for best IC performance
NXP BV17 citations79
US7463508B2Dec 9, 2008
SRAM test method and SRAM test arrangement to detect weak cells
NXP BV10 citations78
US7457971B2Nov 25, 2008
Monitoring and controlling power consumption in a sequential logic circuit
NXP BV8 citations72
US7332953B2Feb 19, 2008
Circuit and method for controlling the threshold voltage of transistors
NXP BV8 citations71
US9960670B2May 1, 2018
Apparatus for charge recycling
NXP BV4 citations68
US7539589B2May 26, 2009
Testing radio frequency and analogue circuits
NXP BV7 citations68
US11461642B2Oct 4, 2022
Apparatus for processing a signal
NXP BV4 citations67
US11567770B2Jan 31, 2023
Human-machine-interface system comprising a convolutional neural network hardware accelerator
NXP BV3 citations66
US10732698B2Aug 4, 2020
Event-based power manager
NXP BV2 citations65
US7886259B2Feb 8, 2011
Method and circuit arrangement for determining power supply noise
NXP BV6 citations61
US10739846B2Aug 11, 2020
Closed-loop adaptive voltage, body-biasing and frequency scaling
NXP BV1 citations59
US11995442B2May 28, 2024
Processor having a register file, processing unit, and instruction sequencer, and operable with an instruction set having variable length instructions and a table that maps opcodes to register file addresses
NXP BV1 citations57
US8988264B2Mar 24, 2015
Analogue to digital converter
NXP BV2 citations56
US7256645B2Aug 14, 2007
Suppression of noise in an integrated circuit
NXP BV2 citations53
US9419592B2Aug 16, 2016
Variability resistant circuit element and signal processing method
NXP BV1 citations52
US7671618B2Mar 2, 2010
Analog IC having test arrangement and test method for such an IC
NXP BV1 citations49
US7477110B2Jan 13, 2009
Method and device for testing a phase locked loop
NXP BV0 citations41
US9996145B2Jun 12, 2018
Shared interrupt multi-core architecture for low power applications
NXP BV0 citations37