Inventor

KALAVADE PRANAV

US94 patents

⚠️ This page may combine multiple inventors who share the name “KALAVADE PRANAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KALAVADE PRANAV

INTEL CORP

Resuming storage die programming after power loss

Coarse pass and fine pass multi-level NVM programming

Concurrent memory operations for read operation preemption

Method and apparatus for protecting lower page data during programming in NAND flash

Erase and soft program for vertical NAND flash

Methods and apparatus to preserve data of a solid state drive during a power loss event

Defective bit line management in connection with a memory access

Method and system for reducing program disturb degradation in flash memory

Method and apparatus for reducing data program completion overhead in NAND flash

Achieving consistent read times in multi-level non-volatile memory

Dynamically compensating for degradation of a non-volatile memory device

Multi-pulse programming for memory

Program VT spread folding for NAND flash memory programming

Interleaved all-level programming of non-volatile memory

Methods and apparatus to preserve data of a solid state drive during a power loss event

Erase and soft program for vertical NAND flash

Segmented erase in memory

Apparatus and method for mapping binary to ternary and its reverse

Managing solid state drive defect redundancies at sub-block granularity

Data storage device with operation based on temperature difference

Achieving consistent read times in multi-level non-volatile memory

Techniques to recover data using exclusive OR (XOR) parity information

Performing read operations on a memory device

Apparatus and method for detecting and mitigating bit-line opens in flash memory

Defect management policies for NAND flash memory

Apparatuses, systems, and methods for heating a memory device

Boosted bitlines for storage cell programmed state verification in a memory array

Program verification time reduction in non-volatile memory devices

System and method for performing a concurrent multiple page read of a memory array

Defective bit line management in connection with a memory access

Method and system for reducing program disturb degradation in flash memory

MICRON TECHNOLOGY INC

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Programming memories with multi-level pass signal

Operation of a memory device during programming

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Programming memories with multi-level pass signal

Buffer operations in memory

Programming memories with multi-level pass signal

Configuration of a memory device for programming memory cells

Configuration of a memory device for programming memory cells

AGERE SYSTEMS INC

Method of making ultra thin body vertical replacement gate MOSFET

Ultra thin body vertical replacement gate MOSFET

GODA AKIRA

Programming memory devices

Drain select gate voltage management

GOLDMAN MATTHEW

Method and system to obtain state confidence data using multistrobe read of a non-volatile memory

Memory cell sensing

KALAVADE PRANAV

Automatic selective slow program convergence

Reconstructing codewords using a side channel

FRANKLIN NATHAN R

Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse