Inventor
THAPLOO ANUPAMA A
US19 patents
Patents
19 patentsUS10062429B1Aug 28, 2018
System, apparatus and method for segmenting a memory array
INTEL CORP15 citations89
US10490170B2Nov 26, 2019
Adaptive multibit bus for energy optimization
INTEL CORP7 citations83
US10290289B2May 14, 2019
Adaptive multibit bus for energy optimization
INTEL CORP7 citations81
US11081091B2Aug 3, 2021
Adaptive multibit bus for energy optimization
INTEL CORP3 citations72
US10409319B2Sep 10, 2019
System, apparatus and method for providing a local clock signal for a memory array
INTEL CORP2 citations72
US10790010B2Sep 29, 2020
System, apparatus and method for segmenting a memory array
INTEL CORP1 citations71
US10418076B2Sep 17, 2019
Apparatus for data retention and supply noise mitigation using clamps
INTEL CORP2 citations71
US10410699B1Sep 10, 2019
Multi-bit pulsed latch including serial scan chain
INTEL CORP2 citations71
US9766827B1Sep 19, 2017
Apparatus for data retention and supply noise mitigation using clamps
INTEL CORP3 citations71
US11636831B2Apr 25, 2023
Adaptive multibit bus for energy optimization
INTEL CORP0 citations62
US11176990B2Nov 16, 2021
System, apparatus and method for segmenting a memory array
INTEL CORP0 citations61
US10333379B2Jun 25, 2019
Power switching circuitry including power-up control
INTEL CORP1 citations56
US10587244B2Mar 10, 2020
Pulse triggered flip flop
INTEL CORP0 citations52
US10158346B2Dec 18, 2018
Pulse triggered flip flop
INTEL CORP0 citations52
US10817012B2Oct 27, 2020
System, apparatus and method for providing a local clock signal for a memory array
INTEL CORP0 citations51
US10754809B2Aug 25, 2020
Reducing aging of register file keeper circuits
INTEL CORP0 citations50
US10347324B2Jul 9, 2019
System, apparatus and method for segmenting a memory array
INTEL CORP0 citations50
US10324721B2Jun 18, 2019
Reducing aging of register file keeper circuits
INTEL CORP0 citations50
US10762877B2Sep 1, 2020
System, apparatus and method for reducing voltage swing on an interconnect
INTEL CORP0 citations42