Inventor

ERVIN JOSEPH

US64 patents

⚠️ This page may combine multiple inventors who share the name “ERVIN JOSEPH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ERVIN JOSEPH

IBM

Asymmetric FET

Metal trench capacitor and improved isolation and methods of manufacture

Recessed single crystalline source and drain for semiconductor-on-insulator devices

Metal trench capacitor and improved isolation and methods of manufacture

Multilayer MIM capacitor

Rare-earth oxide isolated semiconductor fin

Multilayer MIM capacitor

Embedded DRAM for extremely thin semiconductor-on-insulator

Lateral epitaxial grown SOI in deep trench structures and methods of manufacture

Metal trench capacitor and improved isolation and methods of manufacture

Asymmetric FET

Metal trench capacitor and improved isolation and methods of manufacture

Asymmetric FET

Method of forming semiconductor fins on SOI substrate

Self-aligned devices and methods of manufacture

GLOBALFOUNDRIES INC

Method of forming substrate contact for semiconductor on insulator (SOI) substrate

Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench integration with fins

Nanochannel electrode devices

Electrical and optical via connections on a same chip

Electrical and optical via connections on a same chip

Nanochannel electrode devices

Structure to prevent deep trench moat charging and moat isolation fails

Sublithographic width finFET employing solid phase epitaxy

Deep trench capacitor

Method of forming substrate contact for semiconductor on insulator (SOI) substrate

CHENG KANGGUO

Isolation in CMOSFET devices utilizing buried air bags

Deep trench capacitor

Multilayer MIM capacitor

Rare-earth oxide isolated semiconductor fin

Spacer isolation in deep trench

Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate

BOOTH JR ROGER A

Metal trench capacitor and improved isolation and methods of manufacture

Self-aligned strap for embedded capacitor and replacement gate devices

Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate

Self-aligned devices and methods of manufacture

Embedded DRAM for extremely thin semiconductor-on-insulator

Forming implanted plates for high aspect ratio trenches using staged sacrificial layer removal

COVENTOR INC

Static random-access memory cell design

Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment

System and method for performing depth-dependent oxidation modeling in a virtual fabrication environment

ERVIN JOSEPH

Method of forming a buried plate by ion implantation

Lateral epitaxial grown SOI in deep trench structures and methods of manufacture

Lateral epitaxial grown SOI in deep trench structures and methods of manufacture

PEI CHENGWEN

Structure and method to fabricate a body contact

Structure and method to fabricate pFETS with superior GIDL by localizing workfunction

WANG GENG

Recessed single crystalline source and drain for semiconductor-on-insulator devices

Method of forming substrate contact for semiconductor on insulator (SOI) substrate

COMPAQ COMPUTER CORP

Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU&#39;S with write-back caches

DIGITAL EQUIPMENT CORP

Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches

TODI RAVI M

Structure and method for topography free SOI integration

Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches