Inventor

PARRIES PAUL C

US47 patents

⚠️ This page may combine multiple inventors who share the name “PARRIES PAUL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARRIES PAUL C

IBM

Method for providing silicide bridge contact between silicon regions separated by a thin dielectric

Low-cost deep trench decoupling capacitor device and process of manufacture

Concurrent refresh mode with distributed row address counters in an embedded DRAM

Deep trench capacitor in a SOI substrate having a laterally protruding buried strap

Self-aligned contact for closely spaced transistors

Method of self-aligning a trench isolation structure to an implanted well region

Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits

DRAM having deep trench capacitors with lightly doped buried plates

Collarless trench DRAM device

Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization

SOI deep trench capacitor employing a non-conformal inner spacer

Providing isolation for wordline passing over deep trench capacitor

Differential and hierarchical sensing for memory circuits

Low energy ion implantation of a junction butting region

Polysilicon/metal contact resistance in deep trench

Command multiplier for built-in-self-test

System and method for disconnecting a portion of an integrated circuit

Low power manager for standby operation of memory system

Low power manager for standby operation of a memory system

Methods to control the threshold voltage of a deep trench corner device

Quantum conductive recrystallization barrier layers

Differential and hierarchical sensing for memory circuits

Differential and hierarchical sensing for memory circuits

CAM cell with interdigitated search and bit lines

Method of forming thermally stable polycrystal to single crystal electrical contact structure

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

Method of fabricating isolated capacitors and structure thereof

Method of fabricating isolated capacitors and structure thereof

Reduced corner leakage in SOI structure and method

WANG GENG

Through-gate implant for body dopant

Method to reduce threshold voltage variability with through gate well implant

Method to reduce threshold voltage variability with through gate well implant

GLOBALFOUNDRIES INC

Correcting for stress induced pattern shifts in semiconductor manufacturing

Asymmetric stressor DRAM

KWON OH-JUNG

Method of fabricating isolated capacitors and structure thereof

Method of fabricating isolated capacitors and structure thereof

DUBE ABHISHEK

Structure and method for forming isolation and buried plate for trench capacitor

Structure and method for forming isolation and buried plate for trench capacitor

ERVIN JOSEPH

Structure and method to control bottom corner threshold in an SOI device

Reduced corner leakage in SOI structure and method

CHENG KANGGUO

Isolation in CMOSFET devices utilizing buried air bags

(unassigned)

Method of depositing conductors in high aspect ratio apertures using a collimator

FRIED DAVID M

FET structures with trench implantation to improve back channel leakage and body resistance

CHUDZIK MICHAEL P

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

BRODSKY MARYJANE

Deep trench capacitor in a SOI substrate having a laterally protruding buried strap

PARRIES PAUL C

Semiconductor structure having wide and narrow deep trenches with different materials

MESSENGER BRIAN W

Polysilicon/metal contact resistance in deep trench