Inventor
REARICK JEFF
US16 patents
⚠️ This page may combine multiple inventors who share the name “REARICK JEFF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AGILENT TECHNOLOGIES INC
13 patentsUS6715105B1Mar 30, 2004
Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port
AGILENT TECHNOLOGIES INC98 citations97
US6708139B2Mar 16, 2004
Method and apparatus for measuring the quality of delay test patterns
AGILENT TECHNOLOGIES INC56 citations96
US6865706B1Mar 8, 2005
Apparatus and method for generating a set of test vectors using nonrandom filling
AGILENT TECHNOLOGIES INC32 citations92
US6707313B1Mar 16, 2004
Systems and methods for testing integrated circuits
AGILENT TECHNOLOGIES INC34 citations92
US6396312B1May 28, 2002
Gate transition counter
AGILENT TECHNOLOGIES INC21 citations92
US6653957B1Nov 25, 2003
SERDES cooperates with the boundary scan test technique
AGILENT TECHNOLOGIES INC67 citations91
US6380780B1Apr 30, 2002
Integrated circuit with scan flip-flop
AGILENT TECHNOLOGIES INC33 citations90
US6721920B2Apr 13, 2004
Systems and methods for facilitating testing of pad drivers of integrated circuits
AGILENT TECHNOLOGIES INC28 citations87
US6239607B1May 29, 2001
Simulation-based method for estimating leakage currents in defect-free integrated circuits
AGILENT TECHNOLOGIES INC20 citations83
US6763486B2Jul 13, 2004
Method and apparatus of boundary scan testing for AC-coupled differential data paths
AGILENT TECHNOLOGIES INC9 citations74
US6944837B2Sep 13, 2005
System and method for evaluating an integrated circuit design
AGILENT TECHNOLOGIES INC3 citations60
US6895562B2May 17, 2005
Partitioning integrated circuit hierarchy
AGILENT TECHNOLOGIES INC2 citations59
US6737858B2May 18, 2004
Method and apparatus for testing current sinking/sourcing capability of a driver circuit
AGILENT TECHNOLOGIES INC1 citations51