Inventor

AFGHAHI MORTEZA CYRUS

US62 patents

⚠️ This page may combine multiple inventors who share the name “AFGHAHI MORTEZA CYRUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AFGHAHI MORTEZA CYRUS

BROADCOM CORP

Memory architecture with single-port cell and dual-port (read and write) functionality

Memory module with hierarchical functionality

Oscillator having multi-phase complementary outputs

Asynchronously resettable decoder for a semiconductor memory

Oscillator having multi-phase complementary outputs

Sense amplifier with offset cancellation and charge-share limited swing drivers

Refresh techniques for memory data retention

Asynchronously-resettable decoder with redundancy

Oscillator having multi-phase complementary outputs

Sense amplifier with offset cancellation and charge-share limited swing drivers

Limited swing driver circuit

Programmable refresh scheduler for embedded DRAMs

Very dense SRAM circuits

Pseudo differential sensing method and apparatus for DRAM cell

Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)

Programmable refresh scheduler for embedded DRAMs

Block redundancy implementation in hierarchical rams

Memory architecture with single-port cell and dual-port (read and write) functionality

Sense amplifier with offset cancellation and charge-share limited swing drivers

Circuit technique for high speed low power data transfer bus

Asynchronously-resettable decoder with redundancy

Sense amplifier with adaptive reference generation

Limited swing driver circuit

Single-ended sense amplifier with sample-and-hold reference

Circuit technique for high speed low power data transfer bus

Diffusion replica delay circuit

Single-ended sense amplifier with sample-and-hold reference

Content addressable memory cell techniques

Memory architecture with single-port cell and dual-port (read and write) functionality

Sense amplifier with adaptive reference generation

Asynchronously-resettable decoder with redundancy

Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)

Non-volatile memory cell techniques

Dense content addressable memory cell

Sense amplifier with adaptive reference generation

Diffusion replica delay circuit method

High speed flip-flop

High precision delay measurement circuit

High speed flip-flop

Circuit technique for high speed low power data transfer bus

Very dense SRAM circuits

NOVELICS LLC

Single-poly non-volatile memory cell

One-time-programmable memory

Low-power CAM cell

DRAM density enhancements

DRAM architecture

DRAM with reduced power consumption

Single-poly non-volatile memory cell

AFGHAHI MORTEZA CYRUS

Single-ended sense amplifier with sample-and-hold reference

NOVELIES LLC

Memory row and column redundancy