Inventor
PAREDES JOSE A
US9 patents
Patents
9 patentsUS9985655B2May 29, 2018
Generating ECC values for byte-write capable registers
IBM6 citations83
US9985656B2May 29, 2018
Generating ECC values for byte-write capable registers
IBM7 citations83
US9940133B2Apr 10, 2018
Operation of a multi-slice processor implementing simultaneous two-target loads and stores
IBM6 citations82
US9934033B2Apr 3, 2018
Operation of a multi-slice processor implementing simultaneous two-target loads and stores
IBM8 citations82
US7073106B2Jul 4, 2006
Test method for guaranteeing full stuck-at-fault coverage of a memory array
IBM18 citations81
US10176038B2Jan 8, 2019
Partial ECC mechanism for a byte-write capable register
IBM2 citations72
US7561489B2Jul 14, 2009
System and method of selective row energization based on write data
IBM0 citations51
US7379348B2May 27, 2008
System and method of selective row energization based on write data
IBM0 citations51
US9766975B2Sep 19, 2017
Partial ECC handling for a byte-write capable register
IBM0 citations41