Inventor

WHISENHUNT GARY L

US20 patents

⚠️ This page may combine multiple inventors who share the name “WHISENHUNT GARY L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WHISENHUNT GARY L

FREESCALE SEMICONDUCTOR INC

Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation

Interrupt controller for accelerated interrupt handling in a data processing system and method thereof

Cache locking device and methods thereof

Debug instruction for use in a data processing system

Interprocessor message transmission via coherency-based interconnect

Instruction for conditionally yielding to a ready thread based on priority criteria

Multiple address and arithmetic bit-mode data processing device and methods thereof

Method and system for data transfers across different address spaces

MOYER WILLIAM C

Qualification of conditional debug instructions based on address

Programmable error actions for a cache in a data processing system

Data processor for processing a decorated storage notify

Permissions checking for data processing instructions

Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation

MARIETTA BRYAN D

Interrupt priority management using partition-based priority blocking processor registers

Processor interrupt interface with interrupt partitioning and virtualization enhancements

Virtualized instruction extensions for system partitioning

Virtualized interrupt delay mechanism

HOLLOWAY DAVID C

Forward progress mechanism for a multithreaded processor

SNYDER MICHAEL D

Polling using reservation mechanism

BRUCE KLAS M

Thread de-emphasis instruction for multithreaded processor