Inventor
HUM HERBERT H J
US25 patents
⚠️ This page may combine multiple inventors who share the name “HUM HERBERT H J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS6922756B2Jul 26, 2005
Forward state for use in cache coherency in a multiprocessor system
INTEL CORP57 citations96
US6078992AJun 20, 2000
Dirty line cache
INTEL CORP69 citations96
US7360033B2Apr 15, 2008
Hierarchical virtual model of a cache hierarchy in a multiprocessor system
INTEL CORP22 citations92
US7269698B2Sep 11, 2007
Hierarchical virtual model of a cache hierarchy in a multiprocessor system
INTEL CORP20 citations92
US7257693B2Aug 14, 2007
Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system
INTEL CORP28 citations92
US7130969B2Oct 31, 2006
Hierarchical directories for cache coherency in a multiprocessor system
INTEL CORP16 citations92
US7111128B2Sep 19, 2006
Hierarchical virtual model of a cache hierarchy in a multiprocessor system
INTEL CORP16 citations92
US6954829B2Oct 11, 2005
Non-speculative distributed conflict resolution for a cache coherency protocol
INTEL CORP31 citations92
US6675282B2Jan 6, 2004
System and method for employing a global bit for page sharing in a linear-addressed cache
INTEL CORP29 citations92
US6594730B1Jul 15, 2003
Prefetch system for memory controller
INTEL CORP44 citations92
US7716409B2May 11, 2010
Globally unique transaction identifiers
INTEL CORP11 citations84
US7512750B2Mar 31, 2009
Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
INTEL CORP15 citations83
US7434006B2Oct 7, 2008
Non-speculative distributed conflict resolution for a cache coherency protocol
INTEL CORP13 citations83
US7996572B2Aug 9, 2011
Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
INTEL CORP16 citations82
US6560690B2May 6, 2003
System and method for employing a global bit for page sharing in a linear-addressed cache
INTEL CORP8 citations73
US7917646B2Mar 29, 2011
Speculative distributed conflict resolution for a cache coherency protocol
INTEL CORP6 citations71
US7643477B2Jan 5, 2010
Buffering data packets according to multiple flow control schemes
INTEL CORP6 citations63
US7457924B2Nov 25, 2008
Hierarchical directories for cache coherency in a multiprocessor system
INTEL CORP3 citations63
US7203825B2Apr 10, 2007
Sharing information to reduce redundancy in hybrid branch prediction
INTEL CORP5 citations63
US6990551B2Jan 24, 2006
System and method for employing a process identifier to minimize aliasing in a linear-addressed cache
INTEL CORP6 citations63
US7783809B2Aug 24, 2010
Virtualization of pin functionality in a point-to-point interface
INTEL CORP2 citations62
US8885673B2Nov 11, 2014
Interleaving data packets in a packet-based communication system
INTEL CORP0 citations52
US7921251B2Apr 5, 2011
Globally unique transaction identifiers
INTEL CORP0 citations52