Inventor
MULLA DEAN A
US26 patents
⚠️ This page may combine multiple inventors who share the name “MULLA DEAN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEWLETT PACKARD CO
9 patentsUS6185660B1Feb 6, 2001
Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss
HEWLETT PACKARD CO84 citations98
US6427188B1Jul 30, 2002
Method and system for early tag accesses for lower-level caches in parallel with first-level cache
HEWLETT PACKARD CO67 citations96
US6539457B1Mar 25, 2003
Cache address conflict mechanism without store buffers
HEWLETT PACKARD CO58 citations95
US5870387AFeb 9, 1999
Method and apparatus for initializing a ring
HEWLETT PACKARD CO26 citations92
US5860095AJan 12, 1999
Conflict cache having cache miscounters for a computer memory system
HEWLETT PACKARD CO40 citations92
US5696939ADec 9, 1997
Apparatus and method using a semaphore buffer for semaphore instructions
HEWLETT PACKARD CO21 citations92
US6507892B1Jan 14, 2003
L1 cache memory
HEWLETT PACKARD CO28 citations91
US6427189B1Jul 30, 2002
Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline
HEWLETT PACKARD CO25 citations91
US6470374B1Oct 22, 2002
Carry look-ahead for bi-endian adder
HEWLETT PACKARD CO8 citations72
INTEL CORP
9 patentsUS6272597B1Aug 7, 2001
Dual-ported, pipelined, two level cache system
INTEL CORP60 citations95
US6418521B1Jul 9, 2002
Hierarchical fully-associative-translation lookaside buffer structure
INTEL CORP60 citations93
US6105115AAug 15, 2000
Method and apparatus for managing a memory array
INTEL CORP39 citations93
US6427191B1Jul 30, 2002
High performance fully dual-ported, pipelined cache design
INTEL CORP15 citations84
US7159046B2Jan 2, 2007
Method and apparatus for configuring communication between devices in a computer system
INTEL CORP17 citations81
US6453427B2Sep 17, 2002
Method and apparatus for handling data errors in a computer system
INTEL CORP13 citations71
US7376775B2May 20, 2008
Apparatus, system, and method to enable transparent memory hot plug/remove
INTEL CORP2 citations60
US6826573B1Nov 30, 2004
Method and apparatus for queue issue pointer
INTEL CORP4 citations58
US6832308B1Dec 14, 2004
Apparatus and method for instruction fetch unit
INTEL CORP5 citations54
HEWLETT PACKARD DEVELOPMENT CO
6 patentsUS6591393B1Jul 8, 2003
Masking error detection/correction latency in multilevel cache transfers
HEWLETT PACKARD DEVELOPMENT CO17 citations92
US6557078B1Apr 29, 2003
Cache chain structure to implement high bandwidth low latency cache memory subsystem
HEWLETT PACKARD DEVELOPMENT CO32 citations92
US6687262B1Feb 3, 2004
Distributed MUX scheme for bi-endian rotator circuit
HEWLETT PACKARD DEVELOPMENT CO31 citations91
US6704820B1Mar 9, 2004
Unified cache port consolidation
HEWLETT PACKARD DEVELOPMENT CO13 citations83
US6647464B2Nov 11, 2003
System and method utilizing speculative cache access for improved performance
HEWLETT PACKARD DEVELOPMENT CO13 citations82
US6874116B2Mar 29, 2005
Masking error detection/correction latency in multilevel cache transfers
HEWLETT PACKARD DEVELOPMENT CO4 citations62