Inventor
SUGINO RINJI
US34 patents
⚠️ This page may combine multiple inventors who share the name “SUGINO RINJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SPANSION LLC
9 patentsUS7163860B1Jan 16, 2007
Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device
SPANSION LLC25 citations92
US7354826B1Apr 8, 2008
Method for forming memory array bitlines comprising epitaxially grown silicon and related structure
SPANSION LLC12 citations84
US7151028B1Dec 19, 2006
Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability
SPANSION LLC8 citations73
US7297592B1Nov 20, 2007
Semiconductor memory with data retention liner
SPANSION LLC2 citations63
US7220643B1May 22, 2007
System and method for gate formation in a semiconductor device
SPANSION LLC3 citations62
US9493874B2Nov 15, 2016
Distribution of gas over a semiconductor wafer in batch processing
SPANSION LLC1 citations52
US9252026B2Feb 2, 2016
Buried trench isolation in integrated circuits
SPANSION LLC0 citations52
US7998846B2Aug 16, 2011
3-D integrated circuit system and method
SPANSION LLC0 citations51
US9252221B2Feb 2, 2016
Formation of gate sidewall structure
SPANSION LLC0 citations48
FASL LLC
5 patentsUS7033957B1Apr 25, 2006
ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices
FASL LLC62 citations96
US6949481B1Sep 27, 2005
Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device
FASL LLC50 citations92
US6884681B1Apr 26, 2005
Method of manufacturing a semiconductor memory with deuterated materials
FASL LLC31 citations92
US6803265B1Oct 12, 2004
Liner for semiconductor memories and manufacturing method therefor
FASL LLC15 citations84
US7074677B1Jul 11, 2006
Memory with improved charge-trapping dielectric layer
FASL LLC3 citations63
CYPRESS SEMICONDUCTOR CORP
5 patentsUS10020317B2Jul 10, 2018
Memory device with multi-layer channel and charge trapping layer
CYPRESS SEMICONDUCTOR CORP7 citations82
US9831114B1Nov 28, 2017
Self-aligned trench isolation in integrated circuits
CYPRESS SEMICONDUCTOR CORP2 citations73
US9437470B2Sep 6, 2016
Self-aligned trench isolation in integrated circuits
CYPRESS SEMICONDUCTOR CORP3 citations73
US11430689B2Aug 30, 2022
Inter-layer insulator for electronic devices and apparatus for forming same
CYPRESS SEMICONDUCTOR CORP0 citations62
US10256137B2Apr 9, 2019
Self-aligned trench isolation in integrated circuits
CYPRESS SEMICONDUCTOR CORP0 citations52
FUJITSU LTD
4 patentsUS5578133ANov 26, 1996
Dry cleaning process for cleaning a surface
FUJITSU LTD32 citations92
US5725677AMar 10, 1998
Dry cleaning process for cleaning a surface
FUJITSU LTD16 citations82
US5909048AJun 1, 1999
Micro-machining minute hollow using native oxide membrane
FUJITSU LTD6 citations74
US5662814ASep 2, 1997
Micro-machining minute hollow using native oxide membrane
FUJITSU LTD12 citations74
SUGINO RINJI
4 patentsUS8809206B2Aug 19, 2014
Patterned dummy wafers loading in batch type CVD
SUGINO RINJI3 citations60
US8647969B1Feb 11, 2014
Method for forming a semiconductor layer with improved gap filling properties
SUGINO RINJI0 citations47
US8133801B1Mar 13, 2012
Method for forming a semiconducting layer with improved gap filling properties
SUGINO RINJI0 citations47
US8415734B2Apr 9, 2013
Memory device protection layer
SUGINO RINJI0 citations39
ADVANCED MICRO DEVICES INC
3 patentsUS6670241B1Dec 30, 2003
Semiconductor memory with deuterated materials
ADVANCED MICRO DEVICES INC79 citations98
US6765254B1Jul 20, 2004
Structure and method for preventing UV radiation damage and increasing data retention in memory cells
ADVANCED MICRO DEVICES INC30 citations92
US7026211B1Apr 11, 2006
Semiconductor component and method of manufacture
ADVANCED MICRO DEVICES INC4 citations62