Inventor

COLOMBO LUIGI

US133 patents

⚠️ This page may combine multiple inventors who share the name “COLOMBO LUIGI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COLOMBO LUIGI

TEXAS INSTRUMENTS INC

Metal gate MOS transistors and methods for making the same

Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing

Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications

Annealing of high-k dielectric materials

Process for manufacturing dual work function metal gates in a microelectronics device

Gate structure and method

Gate dielectric and method

Encapsulated MOS transistor gate structures and methods for making the same

High temperature interface layer growth for high-k gate dielectric

Anneal sequence for high-κ film property optimization

Methods for sputter deposition of high-k dielectric films

Method of planarizing a conductive plug situated under a ferroelectric capacitor

Protection of tungsten alignment mark for FeRAM processing

Integrated circuit and method

Adhesion promoting sacrificial etch stop layer in advanced capacitor structures

High-k gate dielectric with uniform nitrogen profile and methods for making the same

MOS transistor gates with doped silicide and methods for making the same

Method for fabricating transistor gate structures and gate dielectrics thereof

Encapsulated MOS transistor gate structures and methods for making the same

Method of making multiple work function gates by implanting metals with metallic alloying additives

Hardmask designs for dry etching FeRAM capacitor stacks

Integrated circuit and method

Metal patterning with adhesive hardmask layer

MOS transistor gates with thin lower metal silicide and methods for making the same

Dual work function metal gate integration in semiconductor devices

Refractory metal-based electrodes for work function setting in semiconductor devices

Gate dielectric and method

Gate structure and method

Graphene FET with graphitic interface layer at contacts

Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon

Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation

Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials

Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Method for fabricating split gate transistor device having high-k dielectrics

Integrated circuit and method

Method of forming an FeRAM having a multi-layer hard mask and patterning thereof

Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch

Integrated circuit capacitor and memory

Top surface roughness reduction of high-k dielectric materials using plasma based processes

Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier

Method for integrating high-k dielectrics in transistor devices

Multi-super lattice for switchable arrays

Heterostructure interconnects for high frequency applications

Integration of heat spreader for beol thermal management

Gate structure and method

Structure for dual work function metal gate electrodes by control of interface dipoles

AGILENT TECHNOLOGIES INC

Method of fabricating a ferroelectric memory cell

Contamination control for embedded ferroelectric device fabrication processes

COLOMBO LUIGI

Graphene synthesis by chemical vapor deposition

UNIV TEXAS

Synthesizing graphene from metal-carbon solutions using ion implantation