Inventor

LIN JING-CHENG

TW545 patents

⚠️ This page may combine multiple inventors who share the name “LIN JING-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN JING-CHENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure

Package structure and method

Release film as isolation film in package

Package structures and methods of forming the same

Fan-out PoP structure with inconsecutive polymer layer

Hybrid bonding with through substrate via (TSV)

Package structures and methods of forming the same

Package structures and methods of forming the same

Hybrid bonding with through substrate via (TSV)

Package on package (PoP) bonding structures

3DIC stacking device and method of manufacture

Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure

Integrated fan-out structure with guiding trenches in buffer layer

Integrated fan-out packages and methods of forming the same

Metal oxide layered structure and methods of forming the same

Method for forming hybrid bonding with through substrate via (TSV)

Interconnect structure for package-on-package devices and a method of fabricating

Semiconductor device and method of manufacture

Solution for reducing poor contact in info packages

Backside redistribution layer (RDL) structure

Interconnect structure for wafer level package

TAIWAN SEMICONDUCTOR MFG

Method of fabricating interconnect structure for package-on-package devices

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

Package with a fan-out structure and method of forming the same

Embedded wafer-level bonding approaches

Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process

Fan-out wafer level package structure

Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package

Semiconductor device and manufacturing method thereof

Hybrid bonding with through substrate via (TSV)

Method to solve via poisoning for porous low-k dielectric

Method of barrier-less integration with copper alloy

Method of forming multilayer diffusion barrier for copper interconnections

Barrier-free copper interconnect

Die-on-interposer assembly with dam structure and method of manufacturing the same

Fan out package, semiconductor device and manufacturing method thereof

Integrated circuit structure having dies with connectors

LIN JING-CHENG

3DIC stacking device and method of manufacture

Wafer-level packaging mechanisms

Packaged semiconductor device with a molding compound and a method of forming the same

Packages including active dies and dummy dies and methods for forming the same

Chip-on-Wafer structures and methods for forming the same

YU CHEN-HUA

Interconnect structure for wafer level package

Interposer-on-glass package structures

LIN YUNG-CHI

TSV structures and methods for forming the same

Package systems having interposers with interconnection structures

TAIWAN SEMICONDUCTOR MANFACTURING COMPANY LTD

Packaged semiconductor devices and packaging devices and methods

HUNG JUI-PIN

Packaging methods and structures using a die attach film

SHIH YING-CHING

Embedded 3D interposer structure

HU HSIEN-PIN

Approach for bonding dies onto interposers