Inventor
VAED KUNAL
US23 patents
⚠️ This page may combine multiple inventors who share the name “VAED KUNAL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS7662722B2Feb 16, 2010
Air gap under on-chip passive device
IBM31 citations93
US7005371B2Feb 28, 2006
Method of forming suspended transmission line structures in back end of line processing
IBM22 citations92
US6992344B2Jan 31, 2006
Damascene integration scheme for developing metal-insulator-metal capacitors
IBM24 citations92
US7361950B2Apr 22, 2008
Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric
IBM17 citations91
US7622357B2Nov 24, 2009
Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance
IBM13 citations84
US7439151B2Oct 21, 2008
Method and structure for integrating MIM capacitors within dual damascene processing techniques
IBM12 citations84
US7410894B2Aug 12, 2008
Post last wiring level inductor using patterned plate process
IBM9 citations84
US7394145B2Jul 1, 2008
Methods of fabricating passive element without planarizing and related semiconductor device
IBM10 citations84
US6940117B2Sep 6, 2005
Prevention of Ta2O5 mim cap shorting in the beol anneal cycles
IBM13 citations84
US7910450B2Mar 22, 2011
Method of fabricating a precision buried resistor
IBM7 citations83
US7608909B2Oct 27, 2009
Suspended transmission line structures in back end of line processing
IBM12 citations83
US7545007B2Jun 9, 2009
MOS varactor with segmented gate doping
IBM18 citations83
US7427550B2Sep 23, 2008
Methods of fabricating passive element without planarizing
IBM5 citations74
US7763954B2Jul 27, 2010
Post last wiring level inductor using patterned plate process
IBM7 citations73
US7741698B2Jun 22, 2010
Post last wiring level inductor using patterned plate process
IBM6 citations73
US7573117B2Aug 11, 2009
Post last wiring level inductor using patterned plate process
IBM7 citations73
US7915134B2Mar 29, 2011
Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
IBM6 citations72
US7732294B2Jun 8, 2010
Post last wiring level inductor using patterned plate process
IBM2 citations62
US7691717B2Apr 6, 2010
Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof
IBM5 citations62
US7354872B2Apr 8, 2008
Hi-K dielectric layer deposition methods
IBM0 citations52
US7732295B2Jun 8, 2010
Post last wiring level inductor using patterned plate process
IBM0 citations51