Inventor
LIN MOU-SHIUNG
TW360 patents
⚠️ This page may combine multiple inventors who share the name “LIN MOU-SHIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MEGICA CORP
19 patentsUS7969006B2Jun 28, 2011
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP96 citations99
US7242099B2Jul 10, 2007
Chip package with multiple chips connected by bumps
MEGICA CORP175 citations99
US8021918B2Sep 20, 2011
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP45 citations98
US7902679B2Mar 8, 2011
Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
MEGICA CORP111 citations98
US7465654B2Dec 16, 2008
Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
MEGICA CORP60 citations98
US7420276B2Sep 2, 2008
Post passivation structure for semiconductor chip or wafer
MEGICA CORP62 citations98
US7413929B2Aug 19, 2008
Integrated chip package structure using organic substrate and method of manufacturing the same
MEGICA CORP62 citations98
US7405149B1Jul 29, 2008
Post passivation method for semiconductor chip or wafer
MEGICA CORP67 citations98
US7372161B2May 13, 2008
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP58 citations98
US7271489B2Sep 18, 2007
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP69 citations98
US7230340B2Jun 12, 2007
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP67 citations98
US7470997B2Dec 30, 2008
Wirebond pad for semiconductor chip or wafer
MEGICA CORP66 citations97
US7247932B1Jul 24, 2007
Chip package with capacitor
MEGICA CORP67 citations97
US8004092B2Aug 23, 2011
Semiconductor chip with post-passivation scheme formed over passivation layer
MEGICA CORP42 citations96
US7863654B2Jan 4, 2011
Top layers of metal for high performance IC's
MEGICA CORP16 citations96
US7521812B2Apr 21, 2009
Method of wire bonding over active area of a semiconductor circuit
MEGICA CORP37 citations96
US7498196B2Mar 3, 2009
Structure and manufacturing method of chip scale package
MEGICA CORP47 citations96
US7479450B2Jan 20, 2009
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP18 citations96
US7446035B2Nov 4, 2008
Post passivation interconnection schemes on top of IC chips
MEGICA CORP16 citations96
MEGIC CORP
19 patentsUS6818545B2Nov 16, 2004
Low fabrication cost, fine pitch and high reliability solder bump
MEGIC CORP271 citations99
US6759275B1Jul 6, 2004
Method for making high-performance RF integrated circuits
MEGIC CORP175 citations99
US6756295B2Jun 29, 2004
Chip structure and process for forming the same
MEGIC CORP141 citations99
US6734563B2May 11, 2004
Post passivation interconnection schemes on top of the IC chips
MEGIC CORP79 citations99
US6673698B1Jan 6, 2004
Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
MEGIC CORP100 citations99
US6649509B1Nov 18, 2003
Post passivation metal scheme for high-performance integrated circuit devices
MEGIC CORP156 citations99
US6605528B1Aug 12, 2003
Post passivation metal scheme for high-performance integrated circuit devices
MEGIC CORP151 citations99
US6495442B1Dec 17, 2002
Post passivation interconnection schemes on top of the IC chips
MEGIC CORP207 citations99
US6455885B1Sep 24, 2002
Inductor structure for high performance system-on-chip using post passivation process
MEGIC CORP178 citations99
US6426556B1Jul 30, 2002
Reliable metal bumps on top of I/O pads with test probe marks
MEGIC CORP177 citations99
US6303423B1Oct 16, 2001
Method for forming high performance system-on-chip using post passivation process
MEGIC CORP272 citations99
US7045901B2May 16, 2006
Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board
MEGIC CORP91 citations98
US6800941B2Oct 5, 2004
Integrated chip package structure using ceramic substrate and method of manufacturing the same
MEGIC CORP76 citations98
US6798073B2Sep 28, 2004
Chip structure and process for forming the same
MEGIC CORP78 citations98
US6762115B2Jul 13, 2004
Chip structure and process for forming the same
MEGIC CORP90 citations98
US6746898B2Jun 8, 2004
Integrated chip package structure using silicon substrate and method of manufacturing the same
MEGIC CORP99 citations98
US6593649B1Jul 15, 2003
Methods of IC rerouting option for multiple package system applications
MEGIC CORP77 citations98
US6515369B1Feb 4, 2003
High performance system-on-chip using post passivation process
MEGIC CORP90 citations98
US6350705B1Feb 26, 2002
Wafer scale packaging scheme
MEGIC CORP83 citations98
LIN MOU-SHIUNG
6 patentsUS8503186B2Aug 6, 2013
System-in packages
LIN MOU-SHIUNG143 citations99
US8456856B2Jun 4, 2013
Integrated circuit chip using top post-passivation technology and bottom structure technology
LIN MOU-SHIUNG138 citations98
US8164171B2Apr 24, 2012
System-in packages
LIN MOU-SHIUNG95 citations98
US8148806B2Apr 3, 2012
Multiple chips bonded to packaging structure with low noise and multiple selectable functions
LIN MOU-SHIUNG46 citations97
US6965165B2Nov 15, 2005
Top layers of metal for high performance IC's
LIN MOU-SHIUNG38 citations97
US7482693B2Jan 27, 2009
Top layers of metal for high performance IC's
LIN MOU-SHIUNG24 citations96
(unassigned)
3 patentsUS6356958B1Mar 12, 2002
Integrated circuit module has common function known good integrated circuit die with multiple selectable functions
98 citations99
US6180426B1Jan 30, 2001
High performance sub-system design and assembly
151 citations99
US6103552AAug 15, 2000
Wafer scale packaging scheme
361 citations99
ICOMETRUE CO LTD
1 patentLIN M S
1 patentLEE JIN-YUAN
1 patentShowing the top 50 of 360 patents by PatentIndex Score.