Inventor
KIM JAE-JOON
US74 patents
⚠️ This page may combine multiple inventors who share the name “KIM JAE-JOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS7177177B2Feb 13, 2007
Back-gate controlled read SRAM cell
IBM60 citations98
US7362606B2Apr 22, 2008
Asymmetrical memory cells and memories using the cells
IBM54 citations96
US7313012B2Dec 25, 2007
Back-gate controlled asymmetrical memory cell and memory using the cell
IBM23 citations92
US7642864B2Jan 5, 2010
Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect
IBM35 citations91
US7668035B2Feb 23, 2010
Memory circuits with reduced leakage power and design structures for same
IBM14 citations84
US7492628B2Feb 17, 2009
Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell
IBM10 citations84
US7903450B2Mar 8, 2011
Asymmetrical memory cells and memories using the cells
IBM6 citations74
US7439755B2Oct 21, 2008
Electronic circuit for measurement of transistor variability and the like
IBM8 citations74
US8004305B2Aug 23, 2011
Electronic circuit for measurement of transistor variability and the like
IBM3 citations63
US7787285B2Aug 31, 2010
Independent-gate controlled asymmetrical memory cell and memory using the cell
IBM2 citations63
US7764080B2Jul 27, 2010
Methods of operating an electronic circuit for measurement of transistor variability and the like
IBM2 citations63
US7746709B2Jun 29, 2010
Memory circuit with decoupled read and write bit lines and improved write stability
IBM3 citations63
US7742327B2Jun 22, 2010
Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell
IBM4 citations63
US7495969B2Feb 24, 2009
Techniques for improving write stability of memory with decoupled read and write bit lines
IBM4 citations63
US7417889B2Aug 26, 2008
Independent-gate controlled asymmetrical memory cell and memory using the cell
IBM5 citations63
US7085798B2Aug 1, 2006
Sense-amp based adder with source follower pass gate evaluation tree
IBM4 citations63
US6789099B2Sep 7, 2004
Sense-amp based adder with source follower evaluation tree
IBM6 citations63
US7548822B2Jun 16, 2009
Apparatus and method for determining the slew rate of a signal produced by an integrated circuit
IBM2 citations62
SAMSUNG ELECTRONICS CO LTD
11 patentsUS11562218B2Jan 24, 2023
Neural network accelerator
SAMSUNG ELECTRONICS CO LTD1 citations71
US12493781B2Dec 9, 2025
Neuromorphic processor and operating method thereof
SAMSUNG ELECTRONICS CO LTD0 citations62
US11694067B2Jul 4, 2023
Neuromorphic processor and operating method thereof
SAMSUNG ELECTRONICS CO LTD1 citations62
US11681899B2Jun 20, 2023
Dividing neural networks
SAMSUNG ELECTRONICS CO LTD1 citations62
US11556765B2Jan 17, 2023
Neuromorphic system and operating method thereof
SAMSUNG ELECTRONICS CO LTD0 citations62
US12307358B2May 20, 2025
Neural network accelerator
SAMSUNG ELECTRONICS CO LTD0 citations61
US12125524B2Oct 22, 2024
Electronic device for configuring neural network
SAMSUNG ELECTRONICS CO LTD0 citations61
US11954582B2Apr 9, 2024
Neural network accelerator
SAMSUNG ELECTRONICS CO LTD0 citations61
US11790985B2Oct 17, 2023
Electronic device for configuring neural network
SAMSUNG ELECTRONICS CO LTD0 citations61
US11755897B2Sep 12, 2023
Artificial neural network circuit
SAMSUNG ELECTRONICS CO LTD0 citations61
US11580368B2Feb 14, 2023
Artificial neural network circuit
SAMSUNG ELECTRONICS CO LTD0 citations61
KIM JAE-JOON
4 patentsUS8576000B2Nov 5, 2013
3D chip stack skew reduction with resonant clock and inductive coupling
KIM JAE-JOON24 citations91
US8456247B2Jun 4, 2013
Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)
KIM JAE-JOON9 citations83
US8587357B2Nov 19, 2013
AC supply noise reduction in a 3D stack with voltage sensing and clock shifting
KIM JAE-JOON13 citations82
US8466739B2Jun 18, 2013
3D chip stack skew reduction with resonant clock and inductive coupling
KIM JAE-JOON11 citations82
BANSAL ADITYA
4 patentsUS8139400B2Mar 20, 2012
Enhanced static random access memory stability using asymmetric access transistors and design structure for same
BANSAL ADITYA7 citations83
US9086865B2Jul 21, 2015
Power napping technique for accelerated negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) recovery
BANSAL ADITYA3 citations62
US9064071B2Jun 23, 2015
Usage-based temporal degradation estimation for memory elements
BANSAL ADITYA3 citations62
US8966420B2Feb 24, 2015
Estimating delay deterioration due to device degradation in integrated circuits
BANSAL ADITYA2 citations62
POSTECH RES & BUSINESS DEV FOUND
3 patentsUS11928578B2Mar 12, 2024
Sparsity-aware neural processing unit for performing constant probability index matching and processing method of the same
POSTECH RES & BUSINESS DEV FOUND2 citations71
US11335399B2May 17, 2022
Electronic device for configuring neural network
POSTECH RES & BUSINESS DEV FOUND0 citations61
US11483003B2Oct 25, 2022
Pseudo-complementary logic network
POSTECH RES & BUSINESS DEV FOUND0 citations59
KWANGJU INST SCI & TECH
1 patentPURDUE RESEARCH FOUNDATION
1 patentELECTRONICS AND COMM RES INST
1 patentULSAN NAT INST SCIENCE & TECH UNIST
1 patentSAMSUNG DISPLAY CO LTD
1 patentPOSTECH ACADEMY—INDUSTRY FOUND
1 patentCT ADVANCED SOFT ELECTRONICS
1 patentPOSTECH ACAD IND FOUND
1 patentSEOUL NAT UNIV R&DB FOUNDATION
1 patentKIM DAE HYUN
1 patentShowing the top 50 of 74 patents by PatentIndex Score.