Inventor

RAO RAHUL M

US38 patents

⚠️ This page may combine multiple inventors who share the name “RAO RAHUL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAO RAHUL M

IBM

Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect

Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching

Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks

Electronic circuit for measurement of transistor variability and the like

Technique for mitigating gate leakage during a sleep state

Formal verification driven power modeling and design verification

Formal verification driven power modeling and design verification

Modified standard cells to address fast paths

Electronic circuit for measurement of transistor variability and the like

Methods of operating an electronic circuit for measurement of transistor variability and the like

Memory circuit with decoupled read and write bit lines and improved write stability

Techniques for improving write stability of memory with decoupled read and write bit lines

Dynamic abstract generation and synthesis flow with area prediction

Apparatus and method for determining the slew rate of a signal produced by an integrated circuit

Predictive antenna diode insertion

Scan chain wirelength optimization using Q-learning based reinforcement learning

Electronic circuits including hybrid voltage threshold logical entities

On the fly netlist compression in power analysis

On the fly netlist compression in power analysis

Formal verification driven power modeling and design verification

Static pulsed bus circuit and method having dynamic power supply rail selection

Cross-current power modelling using logic simulation

Cross-current power modelling using logic simulation

Cross-current power modelling using logic simulation

Cross-current power modelling using logic simulation

Balancing cycle stealing with early mode violations

Addressing early mode slack fails by book decomposition

Single corner mixed voltage noise impact on function analysis

Core pairing in multicore systems

Statistical k-means clustering

Delayed equivalence identification

BANSAL ADITYA

Enhanced static random access memory stability using asymmetric access transistors and design structure for same

Usage-based temporal degradation estimation for memory elements

Estimating delay deterioration due to device degradation in integrated circuits

Usage-based temporal degradation estimation for memory elements

Enhanced static random access memory stability using asymmetric access transistors and design structure for same

KUANG JENTE B

Performing logic functions on more than one memory cell within an array of memory cells

KIM JAE-JOON

Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)