Inventor
TAUB MASE J
US37 patents
⚠️ This page may combine multiple inventors who share the name “TAUB MASE J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
33 patentsUS6151229ANov 21, 2000
Charge pump with gated pumped output diode at intermediate stage
INTEL CORP68 citations96
US6160440ADec 12, 2000
Scaleable charge pump for use with a low voltage power supply
INTEL CORP21 citations93
US5822246AOct 13, 1998
Method and apparatus for detecting the voltage on the VCC pin
INTEL CORP48 citations93
US5495453AFeb 27, 1996
Low power voltage detector circuit including a flash memory cell
INTEL CORP104 citations93
US5446408AAug 29, 1995
Method and apparatus for providing selectable sources of voltage
INTEL CORP20 citations93
US5426391AJun 20, 1995
Method and apparatus for providing selectable sources of voltage
INTEL CORP31 citations93
US6463004B2Oct 8, 2002
VPX bank architecture
INTEL CORP18 citations92
US5414669AMay 9, 1995
Method and apparatus for programming and erasing flash EEPROM memory arrays utilizing a charge pump circuit
INTEL CORP53 citations92
US5896338AApr 20, 1999
Input/output power supply detection scheme for flash memory
INTEL CORP26 citations88
US9685204B2Jun 20, 2017
Cross-point memory single-selection write technique
INTEL CORP5 citations84
US9601193B1Mar 21, 2017
Cross point memory control
INTEL CORP12 citations84
US9384831B2Jul 5, 2016
Cross-point memory single-selection write technique
INTEL CORP8 citations84
US9589634B1Mar 7, 2017
Techniques to mitigate bias drift for a memory device
INTEL CORP6 citations82
US5430402AJul 4, 1995
Method and apparatus for providing selectable sources of voltage
INTEL CORP19 citations82
US6532178B2Mar 11, 2003
Reducing level shifter standby power consumption
INTEL CORP10 citations74
US6434073B2Aug 13, 2002
VPX bank architecture
INTEL CORP7 citations74
US10056136B2Aug 21, 2018
Cross-point memory single-selection write technique
INTEL CORP3 citations73
US9792986B2Oct 17, 2017
Phase change memory current
INTEL CORP4 citations73
US9685213B2Jun 20, 2017
Provision of holding current in non-volatile random access memory
INTEL CORP2 citations72
US9543004B1Jan 10, 2017
Provision of holding current in non-volatile random access memory
INTEL CORP2 citations72
US7129770B2Oct 31, 2006
High voltage tracking bias voltage
INTEL CORP10 citations72
US10026460B2Jul 17, 2018
Techniques to mitigate bias drift for a memory device
INTEL CORP2 citations71
US6449211B1Sep 10, 2002
Voltage driver for a memory
INTEL CORP9 citations71
US11276465B1Mar 15, 2022
Device, system and method to float a decoder for deselected address lines in a three-dimensional crosspoint memory architecture
INTEL CORP1 citations63
US6781912B2Aug 24, 2004
Providing protection against transistor junction breakdowns from supply voltage
INTEL CORP2 citations63
US6459645B2Oct 1, 2002
VPX bank architecture
INTEL CORP3 citations63
US9224465B2Dec 29, 2015
Cross-point memory bias scheme
INTEL CORP3 citations62
US11900998B2Feb 13, 2024
Bipolar decoder for crosspoint memory
INTEL CORP1 citations56
US10546634B2Jan 28, 2020
Cross point memory control
INTEL CORP0 citations52
US10497434B2Dec 3, 2019
Cross-point memory single-selection write technique
INTEL CORP0 citations52
US10134468B2Nov 20, 2018
Cross point memory control
INTEL CORP0 citations52
US12230346B2Feb 18, 2025
Cross-point memory read technique to mitigate drift errors
INTEL CORP0 citations51
US10269396B2Apr 23, 2019
Techniques to mitigate bias drift for a memory device
INTEL CORP0 citations50