Inventor

RAJAMANI GURUSHANKAR

US17 patents

⚠️ This page may combine multiple inventors who share the name “RAJAMANI GURUSHANKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAJAMANI GURUSHANKAR

GOOGLE LLC

Vector reductions using shared scratchpad memory

Vector reductions using shared scratchpad memory

Interleaving memory requests to accelerate memory accesses

Off-chip memory backed reliable transport connection cache hardware architecture

Systems for high-speed computing using an optical interchange

Data processing on memory controller

Data processing on memory controller

Data processing on memory controller

Interleaving memory requests to accelerate memory accesses

Memory sparing to improve chip reliability

INTEL CORP

Strategy to verify asynchronous links across chips

Strategy to verify asynchronous links across chips

SHARMA DEBENDRA DAS

Strategy to verify asynchronous links across chips

Increasing Input Output Hubs in constrained link based multi-processor systems

HEWLETT PACKARD DEVELOPMENT CO

Multimodal optimization technique in test generation

QUALCOMM INC

Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media

SHARMA ANIL

Self correction logic for serial-to-parallel converters